Parameterized Cells for 3D IC Multi-Chip Layout Configuration
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Solution Overview
Problem
Current automated design techniques for 3D integrated circuits (ICs) limit the ability to reduce two-dimensional area consumption by only allowing IC components to be placed in a single layout section, despite the use of multiple stacked field effect transistors which increase area requirements.
Innovation Solution
A design system and process design kit (PDK) that includes parameterized cells with customizable parameters and layout configuration options, allowing instances of these cells to be placed entirely on one chip or split across multiple chips, reducing area consumption through multi-chip layout configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of stacked FETs is increased to improve RF switch performance, then performance is improved, but the area occupied by the RF switch increases
Solution Approach 1:
The patent applies dimensionality change by transitioning from a two-dimensional layout to a three-dimensional stacked configuration. Multiple FETs are arranged vertically across different chips in a 3D IC structure, allowing the RF switch to achieve higher performance with more stacked FETs while maintaining a compact two-dimensional footprint. The layout system enables components to be distributed across multiple chips in the vertical dimension, effectively resolving the area-performance tradeoff.
2Productivity
If automated design techniques are used to place IC components, then design efficiency is improved, but the ability to reduce two-dimensional area consumption is limited
Solution Approach 1:
The patent implements dynamics by creating an adaptive layout system that can dynamically adjust component placement strategies based on design requirements. The system transitions from static single-chip placement to dynamic multi-chip placement, allowing automated design tools to optimize both design efficiency and area consumption. The layout configuration can be modified to distribute components across multiple chips, enabling the system to adapt to different area constraints while maintaining automated design efficiency.
Data Source
AI summary
Disclosed are a process design kit (PDK) product and also a design system and a design method that employ the PDK product to layout IC designs including 3D IC designs. The PDK product includes a storage medium and a PDK, including a library of cells, stored thereon. The cells can include parameterized cells (pcells) representing various IC components. The pcells are parameter-customizable and one or more of the pcells are also layout configuration-customizable. Each parameter and layout configuration-customizable pcell includes customization script, which is executable by a processor in response to inputs specific to that pcell and which can cause the processor to place an instance of that pcell with customized parameters in a 3D IC layout according to a selected layout configuration option (e.g., a single-chip layout configuration option or a multi-chip layout configuration option).