PCH SPI Controller for Concurrent Firmware Loading
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Solution Overview
Problem
Increased firmware loading times in cloud servers due to concurrent access bottlenecks at shared flash storage devices lead to slow boot times, which are detrimental for real-time provisioning and costly, with existing solutions either increasing silicon area and BOM costs or being impractical.
Innovation Solution
A multi-socket computing system with a platform controller hub (PCH) utilizing an efficient SPI controller design, restreaming arbiter state machine, optimized router design, and dynamic reprogramming of communications link bridges to provide a high-bandwidth interface for concurrent BIOS and firmware loading, reducing latency and BOM costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple companion dies concurrently access shared flash storage device, then firmware loading parallelism is improved, but interface contention increases causing bottlenecks
Solution Approach 1:
The patent introduces a bridge component as an intermediary between the flash storage device and multiple companion dies. This bridge manages concurrent access requests from multiple CDs, arbitrating and coordinating their access to the shared flash storage interface, thereby reducing direct contention while maintaining parallelism benefits.
Solution Approach 2:
The patent implements firmware image caching by creating copies of frequently accessed firmware images in local memory buffers within the bridge or system memory. Instead of having multiple CDs simultaneously access the flash storage device, the bridge serves cached copies to requesting CDs, eliminating interface contention while maintaining fast firmware loading.
2Speed
If separate interface to shared flash storage is added to each CD socket, then access speed is improved, but silicon area and BOM cost increase
Solution Approach 1:
The patent makes the shared flash storage interface and bridge component serve multiple companion dies simultaneously. Instead of dedicating separate flash interfaces to each CD socket, a single universal interface and bridge infrastructure handles firmware loading for all CDs, reducing silicon area while maintaining access functionality.
Solution Approach 2:
The patent merges multiple flash storage access interfaces into a single shared interface that is arbitrated by a central bridge component. This consolidation reduces the total silicon area required for flash interfaces across all CD sockets while maintaining the ability to service multiple CDs concurrently through the shared resource.
3Reliability
If small ROM is added to each CD to store firmware image, then access reliability is improved, but BOM cost and power requirements increase
Solution Approach 1:
The patent creates software-based copies of firmware images in system memory or bridge buffers rather than hardware ROM on each CD. This virtual copying mechanism provides reliable firmware access without the cost and power overhead of physical ROM components on every companion die.
Solution Approach 2:
The patent replaces the mechanical/physical ROM hardware solution with a software-based firmware loading mechanism. Instead of using physical ROM chips on each CD, the system uses software-controlled firmware image transfer and caching, reducing hardware complexity, BOM cost, and power consumption while maintaining reliability.
Data Source
AI summary
Examples include an apparatus having a communications link bridge coupled to a plurality of processors to control connections between each of the plurality of processors and the apparatus; and a controller coupled to a memory over a memory interface to control access to the memory, the controller configured to, during system initialization, selectively bypass a token requirement for access to the memory for read requests by processors and allow multiple processors to read the memory concurrently.