P-channel DEPMOS Reduced Doping Edge Leakage
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Solution Overview
Problem
Conventional p-channel drain extended metal oxide semiconductor (DEPMOS) devices experience increased impact ionization leakage and parametric shifts due to n-type doping pile-up at the semiconductor surface in the birds beak area, particularly under high back gate bias levels, leading to transient leakage and ON-resistance issues.
Innovation Solution
The implementation of reduced doping finger edge regions in nwell fingers, either through counter-doping with a p-type layer or by masking the nwell implant at the finger ends, reduces excessive n-type doping at the active area/field dielectric boundary, thereby minimizing impact ionization leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If n-type doping is increased in the nwell finger to improve device performance, then device performance is improved, but n-type doping pile-up occurs at the semiconductor surface in the birds beak area causing increased impact ionization leakage
Solution Approach 1:
The patent applies local quality by creating a reduced doping finger edge region at specific locations (finger ends inside the nwell edge close to the active region boundary) while maintaining normal doping in other regions. This is achieved by masking the nwell implant at the finger ends, resulting in a doping concentration gradient that reduces impact ionization leakage at critical locations without compromising overall device performance.
2Ease of manufacture
If conventional nwell finger design is used, then manufacturing is simpler, but transient leakage and parametric shifts occur under high back gate bias levels
Solution Approach 1:
The patent applies preliminary action by pre-defining the reduced doping finger edge region through masking before the nwell implantation process. This preliminary masking step prevents excessive doping at critical locations in advance, thereby preventing transient leakage and parametric shifts before they can occur during device operation under high back gate bias levels.
3Object-generated harmful factors
If n-type doping pile-up is reduced at the finger ends, then impact ionization leakage is reduced, but device complexity increases due to additional masking steps
Solution Approach 1:
The patent merges the reduced doping finger edge region formation with the existing nwell implantation process by using a modified mask pattern. Instead of adding completely separate process steps, the solution integrates the doping reduction into the standard nwell formation flow, thereby reducing impact ionization leakage while minimizing increases in process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces transient leakage and parametric shifts, maintaining device reliability and performance by containing hot carrier effects within the drain drift region rather than the channel region, with minimal impact on intrinsic device characteristics.
Implementation Method 1
A p-doped layer can added (typically by ion implantation) at the finger end inside the nwell edge close to the active region boundary with the field dielectric
Implementation Method 2
A p-doped layer can added (typically by ion implantation) at the finger end inside the nwell edge
Implementation Method 3
Another embodiment has a gap in the nwell implant doping through masking the nwell implant at the finger end inside the nwell edge close to the active region boundary with the field dielectric
Data Source
AI summary
A p-channel drain extended metal oxide semiconductor (DEPMOS) device includes a doped surface layer at least one nwell finger defining an nwell length and width direction within the doped surface layer. A first pwell is on one side of the nwell finger including a p+ source and a second pwell is on an opposite side of the nwell finger including a p+ drain. A gate stack defines a channel region of the nwell finger between the source and drain. A field dielectric layer is on a portion of the doped surface layer defining active area boundaries including a first active area having a first active area boundary including a first active area boundary along the width direction (WD boundary). The nwell finger includes a reduced doping finger edge region over a portion of the WD boundary.