PCI Arbiter Scheduling for High-Importance Data Transmission

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Solution Overview

Problem

In real-time systems requiring high determinism, the variability of traffic timing on a PCI bus can cause transmission issues, where data from high-importance devices may not be transmitted due to the standard PCI arbiter's lack of knowledge about data or device importance and higher-level system timing.

Innovation Solution

Implementing a scheduling system that evaluates the importance of devices and data, using a bus schedule to selectively grant access to the communication bus based on device importance, with a module that receives access requests, evaluates bus schedules, and generates access signals accordingly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If a standard PCI arbiter with a simple fairness algorithm is used, then ease of operation is improved, but reliability of high-importance data transmission deteriorates

Engineering Contradiction:
Improvearbiter operationVSAvoidhigh-importance data transmission
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent introduces importance parameters and timing parameters to the arbitration process. The arbiter evaluates both the importance level of devices/data and timing constraints to make arbitration decisions, transforming the simple fairness algorithm into a multi-parameter decision system that prioritizes critical transmissions while maintaining operational simplicity through structured evaluation criteria.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If a scheduling system that evaluates device importance is implemented, then reliability of data transmission is improved, but device complexity increases

Engineering Contradiction:
Improvedata transmissionVSAvoidarbiter structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The arbitration system is segmented into distinct functional modules: an importance evaluation module that assesses device and data importance levels, a scheduling module that manages the bus schedule, and an arbitration module that makes access decisions. This segmentation allows each module to perform its specific function independently, improving reliability through specialized processing while managing complexity through modular design.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary evaluation of device importance and timing requirements before arbitration decisions are made. The bus schedule is pre-established with timing constraints, and device importance levels are determined in advance, allowing the arbiter to make rapid, reliable decisions without complex real-time analysis during the actual arbitration process.

Inventive Principle:
Principle #10Preliminary action

3Ease of operation

If access is granted based on simple fairness, then ease of operation is improved, but loss of time for high-importance data increases

Engineering Contradiction:
Improveaccess arbitrationVSAvoidhigh-importance data transmission delay
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The arbitration process incorporates timing parameters and importance parameters that allow the system to identify and prioritize time-critical transmissions. By evaluating both the importance level and timing constraints of each access request, the arbiter can allocate bus access in a way that minimizes delays for high-importance data while maintaining simple, rule-based operation.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The system uses feedback from the bus schedule evaluation and device importance assessment to dynamically adjust arbitration decisions. When high-importance data with tight timing constraints is detected, the feedback mechanism triggers prioritized access granting, reducing transmission delays while keeping the overall arbitration process straightforward through systematic feedback loops.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8954643B2Scheduled peripheral component interconnect arbiter
Publication Date: 2015.02.10 HONEYWELL INTERNATIONAL INC
  • US8954643B2 patent drawing
  • US8954643B2 patent drawing
  • US8954643B2 patent drawing

AI summary

Systems and methods are described for arbitrating access of a communication bus. In one embodiment, a method includes performing steps on one or more processors. The steps include: receiving an access request from a device of the communication bus; evaluating a bus schedule to determine an importance of the device based on the access request; and selectively granting access of the communication bus to the device based on the importance of the device.