PCI Device Offset Register Address Translation Unit Memory Access
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Solution Overview
Problem
Conventional PCI systems face performance degradation due to the limited memory access allowed by the base address register (BAR), requiring additional interaction between the PCI host and device when transmitting data larger than the BAR size, which hampers data transmission efficiency.
Innovation Solution
Incorporating an offset register and an address translation unit (ATU) in the PCI device, allowing the PCI host to set an offset and change the accessed memory area, enabling seamless transmission of data larger than the BAR size without additional interaction by dividing the data into parts and shifting the access area accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the PCI host transmits data larger than the PCI BAR size, then the data transmission can be completed, but additional interaction between the PCI host and PCI device is required which deteriorates system performance
Solution Approach 1:
The PCI device memory space is segmented into multiple regions (first memory area and second memory area) that can be independently accessed. The ATU divides the address space into segments that can be mapped to different physical memory regions, allowing the PCI host to access extended memory without requiring multiple separate transactions for address management.
Solution Approach 2:
The ATU acts as an intermediary between the PCI host and the device memory. It translates the PCI host's address requests into appropriate memory access operations, managing the mapping between the limited BAR address space and the extended memory space automatically, thereby eliminating the need for additional host-device interactions.
2Reliability
If the PCI host is allowed to access only limited memory area according to the size of BAR, then resource allocation error is avoided, but the memory access area is restricted which limits data transmission efficiency
Solution Approach 1:
The patent extends the addressable memory space by introducing an additional dimension through the ATU's address translation capability. While the BAR maintains its traditional address space dimensions, the ATU adds a translation layer that maps these addresses to an extended memory space, effectively increasing the accessible memory area without compromising the original address allocation structure.
Solution Approach 2:
The ATU dynamically changes the address translation parameters based on the offset register contents. By modifying the base address and size parameters of the memory window according to the offset value, the system allows the PCI host to access different regions of the extended memory space while maintaining proper resource allocation boundaries.
3Quantity of substance
If the PCI host transmits data in multiple parts with additional interaction, then data larger than BAR size can be transmitted, but the transmission process becomes complex and time-consuming
Solution Approach 1:
The offset register is pre-configured with the appropriate offset value before data transmission begins. The ATU uses this pre-set offset to automatically calculate and switch between different memory areas during the transmission process, eliminating the need for the PCI host to wait for completion messages and re-initiate transactions for each data segment.
Solution Approach 2:
The ATU enables continuous data transmission by maintaining the memory window mapping throughout the entire transmission process. As data flows continuously from the PCI host, the ATU continuously translates addresses to the appropriate memory regions without interrupting the data stream, thereby maintaining uninterrupted useful action during extended memory access.
Data Source
AI summary
A peripheral component interconnect (PCI) device includes a PCI register including a base address register (BAR) configured to determine a first memory area accessed by a PCI host, an offset register configured to store an offset transmitted from the PCI host, an address translation unit (ATU) configured to detect an operation of the PCI host writing the offset to the offset register and to change an accessed area by the PCI host to a second memory area based on the offset stored in the offset register, and a device memory including the first memory area and the second memory area, the device memory configured to store data transmitted from the PCI host and to transmit data stored therein to the PCI host.