PCI Backplane IC Segmentation for Low-Latency SoC Interconnect
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Solution Overview
Problem
Existing solutions for interconnecting Systems on a Chip (SoCs) with independent PCI address spaces face challenges in translating addresses efficiently, leading to increased latency and high costs, particularly when more than two SoCs are interconnected, and often interfere with memory access restrictions.
Innovation Solution
A PCI backplane integrated circuit (IC) with multi-function endpoints (MFN-EPs) and an interconnect communication bus that models SoCs as separate functions, allowing for low-latency, high-throughput communication while enabling selective memory access restrictions by configuring address translation units and base address registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If existing solutions for interconnecting SoCs with independent PCI address spaces are used, then address translation is performed, but latency increases and costs increase particularly when more than two SoCs are interconnected
Solution Approach 1:
The PCI backplane IC is segmented into multiple MFN-EPs, each containing separate input and output ATUs. This segmentation allows independent address translation for each SoC connection, enabling parallel processing of address translations and reducing overall latency when interconnecting multiple SoCs.
Solution Approach 2:
The patent introduces MFN-EPs as intermediary components between SoCs with independent PCI address spaces. These MFN-EPs contain address translation units that mediate the address space differences, enabling transparent communication without requiring complex end-to-end address translation across multiple SoCs.
2Productivity
If existing solutions for interconnecting SoCs are used, then communication between SoCs is enabled, but memory access restrictions are interfered with
Solution Approach 1:
Each MFN-EP is configured with local address translation capabilities specific to its associated SoC. This allows each SoC to have customized address translation rules and memory access restrictions tailored to its specific requirements, enabling high throughput communication while maintaining reliable memory access control.
Solution Approach 2:
The address translation units are pre-configured with translation tables and memory access restriction rules before communication occurs. This preliminary configuration enables the system to enforce memory access restrictions from the outset while maintaining high communication throughput without requiring complex runtime control mechanisms.
3Loss of time
If address translation units are configured for each MFN-EP, then low-latency communication is achieved, but device complexity increases
Solution Approach 1:
Each MFN-EP is designed as a universal module containing both input and output address translation units along with PCI function circuits. This multi-functional design allows the same hardware structure to handle address translation in multiple directions and for multiple SoCs, reducing overall system complexity despite the presence of multiple ATUs.
Data Source
AI summary
An integrated circuit. The integrated circuit comprises an interconnect communication bus and a plurality of peripheral component interconnect (PCI) multi-function endpoints (MFN-EPs) coupled to the interconnect communication bus, each PCI MFN-EP comprising a multiplexing device, a first address translation unit (ATU), and at least one PCI function circuit, each PCI function circuit comprising another ATU and a plurality of base address registers (BARs).