PCI Bridge Memory Read Alias and Command Reissue for Data Transfer
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Solution Overview
Problem
In PCI systems, the bridge device struggles to efficiently manage memory read behavior during mid-data transfer disconnects, leading to wasted bandwidth, latency, and potential data destruction due to lack of length information and prefetchability in Memory Read commands, causing performance limitations and incorrect data retrieval.
Innovation Solution
Implementing a method where a target PCI bridge device prefetches data and sets a bit to recognize subsequent requests as continuations of initial requests, allowing it to send prefetched data, and a master PCI device sets a bit to reissue the original command upon reconnect, enabling efficient data transfer and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the bridge device prefetches data from memory without length information, then data transfer efficiency is improved, but data accuracy deteriorates due to potential data destruction
Solution Approach 1:
The bridge device performs preliminary actions by prefetching data from memory into its buffer before the master device actually requests it. The Memory Read Alias bit enables the bridge to recognize reissued commands as continuations of previous requests, allowing it to have already fetched data waiting in the buffer ready for immediate transfer, thus improving efficiency while maintaining reliability through proper command recognition.
2Quantity of substance
If the bridge device reads more data than requested, then future data availability is improved, but bandwidth usage deteriorates due to fetching unwanted data
Solution Approach 1:
The Memory Read Alias bit provides a feedback mechanism that allows the bridge device to recognize when a master reissues a command. When the bridge sees the same command with the alias bit set, it understands this is a continuation request and can supply data from its buffer without needing to fetch more, thus avoiding wasted bandwidth while maintaining data availability.
3Loss of energy
If the bridge device reads less data than requested, then bandwidth usage is improved, but transfer continuity deteriorates due to disconnections and retries
Solution Approach 1:
The bridge device performs preliminary data fetching into its buffer before the master actually needs it. When the master reissues a command after a disconnect, the bridge already has data ready in the buffer and can continue the transfer without additional memory access, maintaining continuity while using bandwidth efficiently.
4Ease of operation
If the bridge device cannot recognize reissued commands, then command processing simplicity is improved, but performance deteriorates due to repeated data fetching
Solution Approach 1:
The Memory Read Alias bit changes a parameter of the command structure to provide recognition capability. When this bit is set in a reissued command, the bridge can distinguish it as a continuation request rather than a new request, allowing it to supply data from its buffer without refetching, thus improving performance while maintaining relatively simple processing logic.
Data Source
AI summary
A method of controlling memory read behavior in PCI devices includes connecting a master PCI device to a PCI bus. The master PCI device is constructed and arranged to issue a Memory Read Line or a Memory Read Multiple initial command. A target PCI bridge device is connected to the PCI bus. The target PCI bridge device is constructed and arranged to prefetch data from host memory on behalf of the master PCI device and to store the prefetched data. A data transfer transaction is established between the master PCI device and the target PCI bridge device and prefetched data is stored at the target PCI bridge device. A bit is selectively preset in at least one of the PCI devices such that if a disconnect of the transaction occurs, the target PCI bridge device recognizes a subsequent request as a continuation of the initial request and sends prefetched data to the master PCI device.