PCI Bus Burst Transfer Sizing via Configurable Control Registers
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Solution Overview
Problem
The legacy PCI bus protocol lacks the ability to specify transaction sizes, leading to inefficiencies such as latency penalties, wasted bandwidth, and reduced throughput due to guessing the amount of data to be transmitted, especially in multi-agent systems where multiple devices access the bus simultaneously.
Innovation Solution
The introduction of a PCI bus with configurable memory transaction sizes, utilizing control registers to establish windows within a memory map, allowing for precise specification of burst transfer sizes, which enables applications to optimize data transfers based on bandwidth requirements and reduce latency by eliminating unnecessary read requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the PCI master guesses the amount of data to read using Memory Read commands, then the bridge can forward the request to the source, but the latency increases due to multiple read requests and data discarding
Solution Approach 1:
The patent introduces a new parameter (burst transfer size) to the PCI bus protocol that allows specifying the exact amount of data to be transferred in each read request. This changes the fundamental parameter of data transfer specification from implicit guessing to explicit declaration, enabling single-shot reads that eliminate multiple latency-prone requests.
Solution Approach 2:
The patent implements a feedback mechanism where the bridge receives burst transfer size information from the PCI master and uses it to configure the appropriate read request size to the source. This feedback loop ensures that the guessed amount of data matches the actual need, preventing both data discarding and multiple re-read requests.
2Productivity
If the bridge guesses the read data amount, then the PCI master can receive data, but bandwidth is wasted when the guessed amount exceeds the actual need
Solution Approach 1:
The patent modifies the data transfer protocol by introducing a burst transfer size parameter that explicitly specifies the exact amount of data to be transferred. This eliminates the need for bridges to guess data amounts, thereby preventing bandwidth wastage from transferring and discarding excessive data while maintaining high throughput for accurate transfers.
3Adaptability or versatility
If multiple PCI masters access the bus simultaneously in round robin fashion, then each master gets a share, but the latency penalty multiplies and throughput decreases
Solution Approach 1:
The patent introduces burst transfer size as a configurable parameter that allows each PCI master to specify its exact data needs. This enables more efficient arbitration and reduces the number of round-robin cycles needed, as masters can perform larger single-shot reads rather than multiple small reads, thereby improving throughput in multi-agent environments.
4Quantity of substance
If the PCI master makes multiple read requests to obtain needed data, then the data can be retrieved, but the latency penalty accumulates significantly
Solution Approach 1:
The patent changes the data transfer model by introducing explicit burst transfer size specification, allowing the PCI master to retrieve the required data quantity in a single read request rather than multiple smaller requests. This reduces cumulative latency while maintaining the ability to retrieve necessary data quantities.
Data Source
AI summary
Various apparatuses, methods and systems for specifying memory transaction sizes on a PCI bus are disclosed herein. For example, some embodiments of the present invention provide apparatuses for transferring data including a PCI bus, a memory map for memory transactions performed on the PCI bus, and at least one set of control registers adapted to establish at least one window within the memory map. The set of control registers contains an address range for the at least one window within the memory map and a burst transfer size for memory transactions taking place on the PCI bus that are addressed within the address range.