IO Control Circuit for PCI Bus Failure Isolation
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Solution Overview
Problem
Conventional computer systems fail to effectively close a PCI bus that has experienced a failure when multiple buses are connected to a bridge or switch, leading to issues with error recovery and system stability due to increased load capacity and clock skew.
Innovation Solution
A computer system design that includes a device with bus control sections connected to multiple buses, capable of generating error messages and an IO control circuit that closes the affected bus in response, utilizing bus control sections and closing flags to manage bus operations and error recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple PCI buses are connected to a bridge or switch, then the system can support more devices and improve adaptability, but the IO control circuit cannot recognize when a specific bus has failed, worsening system reliability
Solution Approach 1:
The patent divides the monitoring function into separate bus control sections, with each section responsible for a specific PCI bus. When a bus fails, the corresponding bus control section generates an error message that identifies the specific failed bus, enabling the IO control circuit to recognize and close only the affected bus rather than all buses connected to the bridge or switch.
Solution Approach 2:
The patent implements a feedback mechanism where bus control sections continuously monitor their respective buses and generate error messages when failures are detected. This feedback loop enables the IO control circuit to receive real-time status information and take appropriate actions to close failed buses while maintaining operational buses.
2Reliability
If a PCI bus is closed due to failure, then system reliability is improved by preventing error propagation, but system productivity decreases due to operational interruption
Solution Approach 1:
The patent enables independent control of each PCI bus through dedicated bus control sections and closing flags. When a failure occurs on one bus, only that specific bus is closed while other buses remain operational, allowing the system to maintain productivity by continuing to function on healthy buses rather than shutting down the entire system.
Solution Approach 2:
The patent implements a bus recovery mechanism where closed buses can be reopened after failure resolution. The IO control circuit can release the closing flag to reopen a bus that has been recovered from failure, and the system can resume operations on previously closed buses, minimizing overall system downtime and maintaining productivity.
Data Source
AI summary
A computer system includes a plurality of buses; a device connected with the plurality of buses and configured to generate an error message when a failure has occurred on a first bus of the plurality of buses; and an IO control circuit connected with the device and configured to close the first bus in response to the error message transaction. The device includes a plurality of bus control sections respectively connected with said plurality of buses. The IO control circuit transfer a first operation transaction to the first bus through a first bus control section, and closes the first bus in response to the error message transaction in a bus failure operation when the failure has occurred on the first bus.