PCI Bus Power Saving State Transition Control
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Solution Overview
Problem
Existing methods for shifting devices connected to a PCI device to a power saving state can result in access errors or slow access speeds when the CPU attempts to access these devices, leading to potential time-out errors due to unmanaged access restrictions.
Innovation Solution
The CPU transmits an instruction to shift the target device to a power saving state after transitioning the PCI bus to a non-communicable or low-speed communicable state, ensuring that the device is not accessible during the transition, thereby preventing access errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the CPU transmits an instruction to shift the target device to the power saving state while the PCI bus is still communicable, then the power saving state transition is initiated, but the CPU may access the target device during the transition causing access errors or time-out errors
Solution Approach 1:
The PCI bus is transitioned to a non-communicable state before the CPU transmits the power saving state instruction to the target device. This preliminary action prevents the CPU from accessing the target device during the state transition, eliminating access errors and time-out errors while ensuring reliable power management.
2Speed
If the PCI bus remains in a communicable state during the power saving state transition, then the CPU can access the target device, but the access speed becomes slow or the access fails due to the ongoing state transition
Solution Approach 1:
The PCI bus is placed in a non-communicable state before initiating the power saving state transition of the target device. This ensures that no CPU access attempts occur during the transition period, maintaining high access speed when the system returns to normal operation while successfully achieving the power saving state.
3Reliability
If the CPU manages access restrictions to devices connected to the PCI device, then access errors can be prevented, but the system complexity increases due to the need for access management mechanisms
Solution Approach 1:
The access management function is extracted from the CPU and implemented at the PCI bus level. The PCI bus automatically transitions to a non-communicable state during power saving state transitions, eliminating the need for complex CPU-based access restriction management mechanisms while ensuring reliable access control.
Data Source
AI summary
An electronic apparatus includes a semiconductor integrated circuit, another semiconductor integrated circuit connected to the semiconductor integrated circuit via a peripheral component interconnect (PCI) bus, and devices (a hard disk drive (HDD), and a dynamic random access memory (DRAM)) connected to the another semiconductor integrated circuit. The semiconductor integrated circuit transmits a predetermined instruction to the another semiconductor integrated circuit, and the another semiconductor integrated circuit shifts the PCI bus to a non-communicable state or a state communicable at low speed. Thereafter, the another semiconductor integrated circuit shifts the devices (the HDD and the DRAM) to a power saving state.