PCI-E NTB Storage Virtual Appliance I/O Acceleration
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Solution Overview
Problem
Conventional virtualized information handling systems face performance issues with data throughput and latency when communicating storage resources to applications due to limitations in hypervisor driver stacks, particularly when using software-defined storage and multiple hypervisors with different I/O architectures.
Innovation Solution
Implementing a storage virtual appliance that utilizes direct memory access (DMA) and PCI-E Non-Transparent Bridging (NTB) for managed access to local and remote storage resources, enabling processor-integrated I/O engines to accelerate I/O operations and bypass processor involvement in data transfers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional hypervisor driver stacks are used for storage I/O operations in virtualized systems, then software-defined storage can be implemented with multiple hypervisors, but data throughput is limited and latency increases
Solution Approach 1:
The patent introduces a PCI-E Non-Transparent Bridge (NTB) as an intermediary component that enables direct memory access between the storage virtual appliance and the host system memory. The NTB acts as a mediator that bypasses the conventional hypervisor driver stack, allowing DMA operations to occur directly between the storage appliance and memory without processor involvement, thus improving throughput and reducing latency
Solution Approach 2:
The patent replaces the software-based hypervisor driver stack with a hardware-based DMA engine and NTB bridge. This substitution eliminates the need for software processing in the I/O path, using hardware-level direct memory access instead of software-defined storage operations, which significantly improves performance by removing software overhead
2Productivity
If processor-integrated I/O engines are used for DMA operations, then I/O performance is improved, but processor involvement in data transfers increases workload
Solution Approach 1:
The patent extracts the data transfer function from the processor by implementing a dedicated DMA engine that operates independently. The DMA engine is responsible for all data movement between memory and storage devices, completely removing this function from the processor's workload. The processor only needs to initialize the DMA engine and handle high-level I/O requests, while the DMA engine handles the actual data transfer operations
Solution Approach 2:
The DMA engine provides self-service capability by autonomously performing data transfer operations without requiring continuous processor involvement. Once programmed with source and destination addresses and transfer parameters, the DMA engine independently manages the entire data transfer process, including error handling and completion signaling, thereby reducing processor workload while maintaining high I/O performance
3Productivity
If PCI-E NTB is used for address translation between memory spaces, then direct memory access is enabled, but device complexity increases
Solution Approach 1:
The PCI-E NTB is designed with universal functionality that handles multiple I/O operations and address translation tasks through a single standardized interface. The NTB bridge supports various DMA operation modes, different memory address spaces, and multiple storage devices, providing a multi-functional solution that reduces the need for multiple specialized components and simplifies overall system architecture
Data Source
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AI summary
I/O acceleration on a virtualized information handling system includes loading a storage virtual appliance as a virtual machine on a hypervisor. The hypervisor may execute using a first processor and a second processor. The storage virtual appliance is accessed by the hypervisor using a PCI-E device driver that is mapped to a first PCI-E NTB logical endpoint at the first processor. A second PCI-E device driver may be loaded on the storage virtual appliance that accesses the hypervisor and is mapped to a second PCI-E NTB logical endpoint at the second processor. A data transfer operation may be executed between a first memory space that is mapped to the first PCI-E NTB logical endpoint and a second memory space that is mapped to the second PCI-E NTB logical endpoint. The data transfer operation may be a read or a write operation.