PCI-E and PHY Power State Coordination for Network Interface Controllers
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Solution Overview
Problem
As the number of devices connected to data networks increases, there is a growing need for higher data rates, which often results in significant increases in power consumption, particularly affecting battery life in portable devices using Ethernet networks, necessitating ways to reduce power consumption during Ethernet communications.
Innovation Solution
A method and system for optimized power management in network devices supporting PCI-E and Energy Efficient Ethernet (EEE), where the PCI-E core transitions from a low power state to a full power state before receiving an Ethernet packet, and the PHY core initiates a transition from a low power mode to a full power mode, dynamically managing power states to minimize latency and conserve energy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If higher data rates are implemented to meet increasing network demands, then network performance is improved, but power consumption increases significantly
Solution Approach 1:
The patent implements dynamic power management by allowing the network interface controller to transition between different power states (low power and full power) based on network activity conditions. The PCI-E core and PHY core can independently enter or exit low power states, enabling the system to adapt power consumption to actual network traffic requirements rather than operating at fixed high power levels continuously.
Solution Approach 2:
The patent changes the operational parameters of the network interface controller by introducing multiple power states with different performance characteristics. By adjusting power state parameters (L0, L1, L2, L3 for PCI-E core and various power modes for PHY core) based on network activity, the system optimizes the trade-off between data rate performance and power consumption.
2Use of energy by moving object
If the PCI-E core transitions to low power state to save energy, then power consumption is reduced, but latency increases when network activity resumes
Solution Approach 1:
The patent applies preliminary action by having the PHY core transition to full power mode in advance before the PCI-E core needs to process network packets. This staged transition ensures that when network activity arrives at the PCI-E core, the PHY core is already ready, eliminating the latency penalty that would otherwise occur when transitioning from low power state upon packet arrival.
Solution Approach 2:
The patent segments the network interface controller into independent power-managed modules (PCI-E core and PHY core) that can transition between power states independently. This segmentation allows different parts of the system to be in different power states simultaneously, enabling the PHY core to prepare for network activity while the PCI-E core remains in low power state, thus reducing overall latency while maintaining power savings.
3Loss of time
If the PHY core transitions to full power mode before receiving packets, then latency is reduced, but power consumption increases
Solution Approach 1:
The patent implements dynamic coordination between the PHY core and PCI-E core power states. The PHY core transitions to full power mode dynamically based on detection of network activity or in anticipation of traffic, while the PCI-E core maintains low power state until actually needed. This dynamic coordination allows the system to minimize latency only when necessary while maximizing power savings during idle periods.
Data Source
AI summary
Aspects of a method and system for optimized power management for a network device supporting PCI-E and energy efficient Ethernet are provided. In this regard, in a network interface controller that supports energy efficient Ethernet, a PCI-E core may be transitioned from a low power PCI-E state to a full power PCI-E state when a PHY core in the network interface controller initiates transition from a low power mode to a full power mode and before the PHY core receives an Ethernet packet. In another embodiment, the PHY core in the network interface controller may be transitioned from a low power mode to a full power mode when the PCI-E core initiates transition from a low power PCI-E state to a full power PCI-E state, and before the PCI-E core receives a command to send an Ethernet packet.