Distributed Routing Scheme for PCI Express Switches
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Solution Overview
Problem
Existing PCI Express switches face performance bottlenecks due to blocking of data packets and low reusability of intellectual property in routing blocks, as they require knowledge of all ports and re-design when configuration changes occur, leading to inefficient processing and reduced design reusability.
Innovation Solution
A PCI Express switch with a distributed routing scheme, where each port has routing slaves listening to multiple routing information buses, allowing parallel processing and non-blocking routing, and utilizing daisy chains to coordinate routing assertions and handle conflicts, enabling increased design reusability and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a PCI Express switch uses centralized routing logic where all routers know all ports, then routing decisions can be made centrally, but data packets from different ports block each other and processing performance deteriorates
Solution Approach 1:
The patent divides the centralized routing logic into distributed routing slaves at each port. Each routing slave independently processes packets from its associated port, eliminating the bottleneck of centralized processing. This segmentation allows parallel packet processing across multiple ports simultaneously, resolving the performance degradation caused by blocking in centralized architectures.
Solution Approach 2:
The patent introduces a hierarchical routing architecture with multiple levels: local routing decisions at port level, and global routing coordination through routing information buses. This dimensional transformation from flat centralized control to multi-level distributed control enables both local autonomy for performance and global coordination for correctness.
2Reliability
If PCI Express switch routers have knowledge of all ports, then routing decisions are accurate, but when ports are added or removed or topology changes, the routers must be re-designed reducing intellectual property reusability
Solution Approach 1:
The patent segments routing knowledge into port-specific routing slaves rather than requiring all routers to know all ports. Each routing slave maintains routing information only for its local port context, while global routing information is distributed through routing information buses. This segmentation allows independent addition or removal of ports without requiring redesign of existing routing logic, significantly improving design reusability.
Solution Approach 2:
The patent implements dynamic routing information distribution where routing information can be added or removed from the routing information buses as ports are added or removed. The routing slaves dynamically update their knowledge base through listening to routing information buses, eliminating the need for static pre-configured routing tables that require complete redesign upon topology changes.
3Productivity
If each port has routing slaves listening to multiple routing information buses, then parallel processing capability increases, but the complexity of coordinating routing assertions increases
Solution Approach 1:
The patent introduces routing information buses as intermediary communication channels between routing slaves. These buses mediate the coordination of routing assertions by providing a standardized interface for exchanging routing information. This intermediary layer simplifies the coordination complexity by abstracting the communication protocol and providing automatic arbitration mechanisms for handling conflicting routing assertions from multiple ports.
Solution Approach 2:
The patent implements feedback mechanisms where routing slaves listen to routing information buses and adjust their routing decisions based on information from other ports. This feedback loop enables automatic coordination of parallel routing operations, with routing assertions being refined based on real-time information about packet flow and routing state across the switch fabric.
Data Source
AI summary
A Peripheral Component Interconnect (PCI) Express switch is provided. The PCI Express switch includes a first routing information bus connected to the first port; a second routing information bus connected to the second port; a third routing information bus connected to the third port; two routing slaves in the first port, each dedicated to listening to one of the second and the third routing information buses; two routing slaves in the second port, each dedicated to listening to one of the first and the third routing information buses; and two routing slaves in the third port, each dedicated to listening to one of the first and the second routing information buses.