PCI Express Transaction Flow Control via Segmented Memory Queues

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Solution Overview

Problem

In a PCI Express fabric, the lack of adherence to ordering rules for transaction packets can lead to system lock-ups, particularly when non-posted and completion packets block inbound completions, causing potential memory overflow and bottlenecks.

Innovation Solution

The method involves subdividing memory into segments for posted, non-posted, and completion cycles, with posted cycles having the highest priority, ensuring correct ordering and preventing memory overflow by allocating priority based on packet type, thereby facilitating timely packet delivery and avoiding deadlocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If non-posted and completion packets are allowed to occupy memory space, then memory utilization increases, but system lock-ups occur and posted packets are blocked

Engineering Contradiction:
Improvememory utilizationVSAvoidsystem stability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The memory space is segmented into separate queues for different packet types (posted, non-posted, completion). This segmentation allows each packet type to be managed independently, preventing lower-priority packets from blocking higher-priority ones while maintaining overall memory utilization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different priority levels are assigned to different packet types within the memory system. Posted packets are given highest priority, non-posted packets intermediate priority, and completion packets lowest priority. This local quality differentiation ensures that critical posted packets are always processed first while still allowing other packets to occupy memory space.

Inventive Principle:
Principle #3Local quality

2Volume of stationary object

If memory space is shared among all packet types, then storage capacity increases, but ordering rules are violated and deadlocks occur

Engineering Contradiction:
Improvestorage capacityVSAvoidordering compliance
Core Design Contradiction:
Volume of stationary objectVSEase of operation

Solution Approach 1:

The shared memory space is divided into separate queues for posted, non-posted, and completion packets. This segmentation maintains storage capacity while enforcing ordering rules by ensuring that posted packets are always retrieved before non-posted packets, which are retrieved before completion packets.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Packet types are pre-categorized into separate queues upon arrival at the target device. This preliminary classification ensures that when packets are retrieved, the correct ordering is automatically maintained without requiring complex real-time prioritization logic.

Inventive Principle:
Principle #10Preliminary action

3Speed

If priority-based retrieval is implemented, then posted packet delivery speed improves, but memory management complexity increases

Engineering Contradiction:
Improvepacket delivery speedVSAvoidmemory management complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The memory is segmented into separate queues for different packet types, which simplifies priority management. Instead of implementing complex priority algorithms, the system simply retrieves packets from the posted queue first, then the non-posted queue, then the completion queue, reducing management complexity while maintaining high delivery speed for posted packets.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system changes the parameter of packet retrieval from FIFO (first-in-first-out) to priority-based retrieval. By associating each packet type with a fixed priority level, the system achieves fast posted packet delivery without requiring dynamic priority adjustment mechanisms, keeping memory management relatively simple.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8019910B2Transaction flow control in PCI express fabric
Publication Date: 2011.09.13 HEWLETT PACKARD ENTERPRISE DEV LP
  • US8019910B2 patent drawing
  • US8019910B2 patent drawing
  • US8019910B2 patent drawing

AI summary

A computer-executed method for controlling transaction flow in a network comprises communicating transaction packets among a plurality of devices in a network fabric and subdividing a memory into a plurality of memory segments for storing received transaction cycles according to transaction packet type comprising posted, non-posted, and completion cycles. A plurality of transaction cycles are received in the memory segment plurality at a target device and transaction cycle priority is allocated according to transaction packet type wherein posted cycles have highest priority. Cycles are retrieved from the memory segment plurality in an order determined by priority.