PCI-Express Transaction Tagging via Memory Mapping
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Solution Overview
Problem
Conventional data packet routing systems face performance issues due to the need to store and compare 32 different tag values, which consumes significant system resources and requires many clock cycles, impairing overall system performance and limiting the number of outstanding memory-read requests.
Innovation Solution
The system employs memory mapping approaches with transaction ID tag fields to assign tag values to specified addresses in internal memory, using selected bits from these fields to select corresponding transaction parameters, thereby optimizing resource usage and reducing processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional tag value storage and comparison methods are used, then routing accuracy is maintained, but system performance deteriorates due to resource consumption and processing time
Solution Approach 1:
The patent applies preliminary action by pre-storing transaction parameter sets in internal memory at specific addresses corresponding to each tag value. This allows the system to directly access pre-prepared routing parameters instead of performing real-time comparisons, significantly reducing processing time and clock cycles while maintaining routing accuracy.
Solution Approach 2:
The patent transforms the one-dimensional tag value comparison process into a two-dimensional memory addressing scheme. Each tag value is mapped to a specific memory address where its corresponding transaction parameter set is stored. This dimensional transformation enables direct address-based parameter retrieval instead of sequential comparison, improving system performance by eliminating time-consuming comparison operations.
2Adaptability or versatility
If 32 different tag values are stored and compared, then complete transaction parameter coverage is achieved, but device complexity increases
Solution Approach 1:
The patent segments the transaction parameter space by creating distinct parameter sets for each tag value (0-31). Each parameter set is stored at a dedicated memory address, allowing the system to maintain comprehensive transaction parameter coverage while organizing resources in a structured, efficient manner. This segmentation enables direct address-based access without requiring complex comparison logic.
3Measurement precision
If tag value comparison is performed for each data packet, then routing accuracy is maintained, but productivity decreases due to processing overhead
Solution Approach 1:
The patent applies preliminary action by pre-configuring transaction parameter sets in internal memory with each set corresponding to a specific tag value. When a data packet arrives, the system directly uses the tag value to address and retrieve the pre-prepared parameter set, eliminating the need for time-consuming comparison operations while maintaining routing accuracy.
Solution Approach 2:
The patent replaces the mechanical comparison process with a direct memory addressing mechanism. Instead of comparing tag values against stored reference values, the system uses the tag value itself as a memory address to directly retrieve the corresponding transaction parameters. This substitution eliminates iterative comparison operations and significantly improves data packet processing throughput.
Data Source
AI summary
Systems and methods of routing data units such as data packets or data frames that provide improved system performance and more efficient use of system resources. The disclosed systems and methods employ memory mapping approaches in conjunction with transaction ID tag fields from the respective data units to assign each tag value, or at least one range of tag values, to a specified address, or at least one range of specified addresses, for locations in internal memory that store corresponding transaction parameters. The disclosed systems and methods can also apply selected bits from the transaction ID tag fields to selector inputs of one or more multiplexor components for selecting corresponding transaction parameters at data inputs to the multiplexor components. The disclosed systems and methods may be employed in memory-read data transfer transactions to recover the transaction parameters necessary to determine destination addresses for memory locations where the memory-read data are to be transmitted.