PCI Host Bridge Dual Reset Modes for Error Recovery
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Solution Overview
Problem
In high availability computer systems, fatal errors in PCI host bridges (PHBs) cause significant delays due to the time required for reset and reconfiguration, potentially exceeding failover thresholds and leading to unnecessary virtual machine failovers.
Innovation Solution
Implementing a dual reset mode system for PHBs, where a warm reset clears only error and status registers, allowing for quicker recovery using existing configuration data, and a full reset for initialization when necessary, thereby reducing recovery time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a full reset is performed to clear all registers including configuration registers, then the PHB can be completely reinitialized, but the recovery time increases to six to eight seconds
Solution Approach 1:
The patent segments the reset operation into two distinct modes: warm reset and full reset. Warm reset clears only error and status registers while preserving configuration registers, whereas full reset clears all registers including configuration. This segmentation allows the system to choose the appropriate reset depth based on the error type, thereby reducing unnecessary reconfiguration time while maintaining reliable error recovery.
Solution Approach 2:
The patent introduces a parameter (reset mode selection) that changes the behavior of the reset operation. By defining multiple reset modes with different clearing scopes, the system can adjust the reset parameter to match the severity of the error, optimizing the balance between recovery reliability and recovery time.
2Reliability
If the failover threshold is increased to 20 seconds to accommodate PHB recovery time, then unnecessary VM failovers are prevented, but the delay in performing needed failovers increases by eight seconds
Solution Approach 1:
The patent segments the recovery time into two components: warm reset time (shorter) and full reset time (longer). By using warm reset for non-critical errors, the system achieves faster recovery that falls within the original 12-second failover threshold, preventing false failovers without needing to increase the threshold. Full reset is reserved for critical errors where the longer recovery time is acceptable.
Solution Approach 2:
The patent applies partial action by performing only the necessary clearing operations (error and status registers) rather than a complete reset of all registers. This partial reset approach is sufficient for many error conditions and achieves recovery within the original failover threshold, avoiding the need to increase the threshold and its associated delays.
3Reliability
If configuration registers are cleared during reset, then the PHB can be fully reinitialized, but the firmware must reconfigure all configuration registers even when unchanged
Solution Approach 1:
The patent segments the register clearing operation to distinguish between configuration registers and operational registers (error and status registers). By clearing only the operational registers during warm reset and preserving configuration registers, the system eliminates unnecessary reconfiguration steps while maintaining proper PHB reinitialization for the affected operational areas.
Solution Approach 2:
The patent extracts the configuration register clearing operation from the standard reset process. Instead of automatically clearing all registers, the system selectively clears only error and status registers during warm reset, taking out the configuration register clearing step entirely. This extraction eliminates the time-consuming reconfiguration process for unchanged configuration data.
Data Source
AI summary
A PCI host bridge (PHB) includes a warm reset mode and a full reset mode. When a fatal error occurs, the type of fatal error is determined, a reset mode corresponding to that type of fatal error is determined, and a reset corresponding to the reset mode is performed. A full reset clears the error registers, status registers and configuration registers, which then requires the configuration registers to be reconfigured before the PHB can be reinitialized. A warm reset clears the error registers and status registers, but does not clear the configuration registers. A warm reset thus does not require the time to write to the configuration registers, and the PHB can be reinitialized using the existing configuration data in the configuration registers while link training is done in parallel. When initialization of the PHB after a warm reset is not successful, a full reset is performed.