Inter-thread Interrupt via PCI MMIO Write
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Solution Overview
Problem
In some application scenarios, interrupt signal notification between CPUs hosting threads cannot be implemented using traditional inter-processor interrupt (IPI) mechanisms, particularly in virtualization environments and multi-level scheduling systems.
Innovation Solution
A method and apparatus for sending interrupt signals between threads using a PCI device, where a notification message is sent via an MMIO write operation, and the interrupt signal is generated and configured based on the thread's status to be sent to the appropriate processor using configured interrupt configuration information, including options for interrupt handlers, Posted Interrupts, semaphore, or eventfd methods, and considering the thread's kernel mode and running status.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional inter-processor interrupt (IPI) mechanism is used for interrupt signal notification between CPUs, then interrupt signaling is limited to specific scenarios, but it cannot be applied in virtualization environments and multi-level scheduling systems
Solution Approach 1:
The patent introduces a PCI device as an intermediary component between the first thread and second thread. The PCI device receives notification messages via MMIO write operations and generates interrupt signals based on configured interrupt sending manners. This intermediary approach enables interrupt signaling across different execution contexts (host kernel, guest kernel, user mode) where direct IPI cannot be used, thereby improving adaptability while maintaining reliable interrupt delivery.
2Adaptability or versatility
If interrupt signals are sent to all possible thread states, then all threads can be notified, but system overhead increases and vulnerability to denial-of-service attacks increases
Solution Approach 1:
The patent dynamically configures interrupt sending manners based on the target thread's execution context. Different interrupt delivery mechanisms are selected according to whether the thread is in host kernel, guest kernel, or user mode. This dynamic adaptation ensures interrupt signals are delivered appropriately to threads in various states without uniformly applying complex mechanisms to all cases, thereby reducing overall system overhead while maintaining broad thread state coverage.
Solution Approach 2:
The patent changes the parameters of interrupt configuration information based on thread status information. The interrupt configuration includes different sending manners (e.g., direct interrupt, Posted Interrupt, semaphore, eventfd) selected according to the thread's running status. This parameter adjustment allows the system to optimize interrupt delivery for each specific thread state, achieving effective notification without excessive overhead.
3Productivity
If multiple interrupt sending manners are configured based on thread status, then interrupt delivery is optimized for different contexts, but configuration complexity increases
Solution Approach 1:
The patent performs preliminary configuration of interrupt configuration information in the PCI device before interrupt signals need to be sent. The interrupt configuration information, including different sending manners for different thread states, is pre-configured based on expected execution contexts. This preliminary action eliminates the need for complex real-time decision-making during interrupt delivery, improving efficiency while managing configuration complexity through advance preparation.
Data Source
AI summary
Implementations of the present specification provide an inter-thread interrupt signal sending method and apparatus. In the inter-thread interrupt signal sending method, a processor in which a first thread is located sends a notification message to a PCI device via a PCI bus by using an MMIO write operation. The MMIO write operation is implemented based on a virtual space address of the first thread to which a memory address of an MMIO memory of the PCI device is mapped. The PCI device generates an interrupt signal for a second thread in response to receiving the notification message, and sends the interrupt signal to a processor in which the second thread is located based on an interrupt signal sending manner configured in interrupt configuration information of the PCI device. The interrupt configuration information of the PCI device is pre-configured based on status information of the second thread, and the status information of the second thread includes whether the second thread is running or a running status of the second thread.