PCIe Address Aggregation via Breadth-Depth Traversal
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In multi-processor systems, the existing PCIe architecture faces challenges with address allocation and discovery, leading to system conflicts and inefficiencies, particularly when scaling to large numbers of connected devices, which exceeds the number of Base Address Registers (BARs), necessitating improved address aggregation and translation mechanisms.
Innovation Solution
A method for assigning memory addresses in a PCIe network that uses a combined breadth-first and depth-first tree traversal process to enable efficient address aggregation, allowing for contiguous address allocation across the network, and employs Non-Transparent Bridging (NTB) for redundancy and extra connections, translating addresses via a single translation register to manage packet routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional PCIe address allocation is used in multi-processor systems, then standard discovery and configuration software can operate, but system conflicts occur and address space utilization becomes inefficient when scaling to large numbers of devices
Solution Approach 1:
The patent merges multiple PCIe device addresses into a single aggregated address that represents a group of devices. This is achieved by creating an aggregate address structure that can represent multiple individual device addresses, thereby reducing the number of address translations needed and improving address space utilization in multi-processor systems.
Solution Approach 2:
The patent introduces an address translation mechanism that acts as an intermediary between the host processor and multiple PCIe devices. This translation layer aggregates multiple device addresses into fewer translation register entries, reducing the complexity of address management while maintaining full access to individual devices.
2Quantity of substance
If the number of PCIe devices exceeds the number of Base Address Registers (BARs), then device connectivity is maintained, but address translation overhead increases and efficiency decreases
Solution Approach 1:
The patent combines multiple individual device addresses into aggregate address groups, allowing a single translation register entry to represent multiple PCIe devices. This merging approach enables the system to support more connected devices without proportionally increasing the number of translation register entries, thereby maintaining address translation efficiency.
3Ease of operation
If multiple processors attempt to enumerate the entire system simultaneously, then each processor can discover devices independently, but system conflicts occur and the system may become non-functional
Solution Approach 1:
The patent introduces an address aggregation and translation mechanism that serves as an intermediary for device discovery. This mechanism allows multiple processors to independently enumerate devices without conflicts by providing a unified address space view, thereby maintaining both discovery independence and system reliability.
Data Source
AI summary
A peripheral component interconnect express PCI-e network system having a processor for (a) assigning addresses to the PCI-e topology tree, comprising: traversing, at a given level and in a breadth direction, down-link couplings to an interconnection; ascertaining, at the level, which of the down-link couplings are connected to nodes; assigning, at the level, addresses to nodes of ascertained down-link coupling having nodes; and (b) propagating, a level, comprising: traversing, at the level and in a depth direction, down-link couplings to the interconnection of the PCI-e network, ascertaining, at the level, which of the downlink couplings are coupled to other interconnections in the depth direction, consecutively proceeding in the depth direction, to a next level of the down-link coupling of a next interconnection; and alternatively repeating (a) and (b) until the nodes are assigned addresses within the PCI-e tree topology network.