PCIe Address Translation Bypass via Address Space Field
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Solution Overview
Problem
The complexity of address translations between multiple microprocessors and intelligent I/O devices in modern computers, such as those using PCIe interfaces, complicates overall system design and operation due to the need for multiple address translations at each step.
Innovation Solution
The introduction of an address space field with additional bits (e.g., ASEL) to indicate the address space, allowing for simplified handling of address values by bypassing or performing address translations as needed, thereby simplifying system design and operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If address translations are performed at each step between multiple microprocessors and intelligent I/O devices, then address space isolation and correctness are maintained, but system design complexity and operational difficulty increase
Solution Approach 1:
The patent introduces an intermediary mechanism (the address space field with bypass capability) that mediates between different address spaces. By adding an address space field with a bypass bit, the system can selectively skip translation steps when moving between certain address spaces, reducing complexity while maintaining isolation where needed.
Solution Approach 2:
The patent makes the address translation process dynamic by introducing a bypass capability. The system can adaptively choose whether to perform address translation based on the source and destination address spaces, transitioning from a static mandatory-translation model to a dynamic optional-translation model, thereby reducing complexity when bypassing is appropriate.
2Reliability
If multiple address translations are performed at each step, then correct address mapping between disparate address spaces is achieved, but data transfer efficiency and processing speed decrease
Solution Approach 1:
The patent enables skipping unnecessary address translation steps by introducing a bypass mechanism. When the source and destination address spaces have compatible mappings or when translation is unnecessary, the system can rush through the translation process by bypassing it entirely, thereby improving data transfer efficiency without sacrificing correctness when translation is needed.
Solution Approach 2:
The patent performs preliminary determination of whether address translation is needed before executing the data transfer. By checking the address space field and bypass capability in advance, the system can pre-determine the translation requirement and prepare the appropriate translation or bypass path, reducing overhead and improving efficiency.
3Reliability
If address translations are performed in each direction between address spaces, then complete address space isolation is maintained, but the number of translation operations and processing time increase
Solution Approach 1:
The patent allows skipping translation operations in specific directions when the address spaces are compatible or when the bypass bit is set. This selective skipping reduces the number of translation operations and processing time while maintaining address space isolation where translation is actually necessary.
Solution Approach 2:
Instead of universally performing translations in both directions, the patent inverts the approach by allowing bypasses in specific directions when appropriate. This inversion of the default translation behavior reduces processing time without compromising isolation when needed.
Data Source
AI summary
An address space field is used in conjunction with a normal address field to allow indication of an address space for the particular address value. In one instance, one address space value is used to indicate the bypassing of the address translation used between address spaces. A different address space value is designated for conventional operation, where address translations are performed. Other address space values are used to designate different transformations of the address values or the data. This technique provides a simplified format for handling address values and the like between different devices having different address spaces, simplifying overall computer system design and operation.