Address Controller for PCIe Memory Isolation in Logical Partitions
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Solution Overview
Problem
Current systems fail to adequately support the connection of both SR-IOV compliant and non-SR-IOV devices to a single PCIe Root Complex while ensuring that PCIe device memory access requests are contained within the memory range assigned to the controlling logical partition (LPAR).
Innovation Solution
An address controller that receives memory access requests, identifies the type of PCIe device, and corrects the request to ensure access only to the memory range owned by the LPAR controlling the requesting function, using a bit selector and address control unit to determine the correct memory range based on the Requester ID (RID) and address portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single PCIe Root Complex supports both SR-IOV and standard PCIe devices, then device compatibility and resource utilization are improved, but memory access control and LPAR isolation become more difficult to maintain
Solution Approach 1:
The patent introduces an address controller as an intermediary component between PCIe devices and memory. This controller receives memory access requests from both SR-IOV and standard PCIe devices, extracts the requester ID (RID), determines the corresponding LPAR, and validates that the access is within the authorized memory range. This intermediary mechanism enables a single Root Complex to support multiple device types while maintaining strict memory isolation between LPARs.
Solution Approach 2:
The system performs preliminary actions by pre-configuring memory ranges associated with each LPAR and storing these associations in a data structure. Before processing memory access requests, the address controller has already prepared the mapping information, enabling it to quickly validate RID-to-LPAR mappings and enforce memory access boundaries without adding runtime overhead to the memory isolation mechanism.
2Reliability
If separate Root Complexes are used for SR-IOV and standard PCIe devices, then memory access control is simplified, but system complexity and resource utilization deteriorate
Solution Approach 1:
The address controller is designed as a universal component that handles memory access requests from both SR-IOV compliant devices and standard PCIe devices through a single interface. It uses a unified RID extraction and LPAR determination mechanism that works for both device types, eliminating the need for separate Root Complexes while maintaining proper memory access control for all devices.
Solution Approach 2:
The patent merges the functionality of separate Root Complexes into a single unified Root Complex by introducing an address controller that consolidates memory access control for both SR-IOV and standard PCIe devices. This combining approach reduces system complexity while maintaining the reliability of memory access control through centralized RID validation and LPAR-based memory range enforcement.
3Ease of manufacture
If firmware ensures address validity for standard PCIe devices, then implementation simplicity is improved, but support for SR-IOV devices and memory isolation deteriorate
Solution Approach 1:
The address controller serves as an intermediary that replaces firmware-based address validation for standard PCIe devices with a hardware-enforced mechanism. It extracts RID information from all PCIe devices (both SR-IOV and standard), determines the authorized LPAR, and validates memory addresses against the LPAR's assigned range. This hardware intermediary provides unified support for both device types while maintaining strong memory isolation.
Solution Approach 2:
The patent substitutes firmware-based address validation (software/mechanical approach) with a hardware-based address controller that automatically extracts RID information, determines LPAR ownership, and enforces memory access boundaries. This mechanical-to-hardware substitution improves both device support capability and memory isolation effectiveness while maintaining implementation simplicity through dedicated circuitry.
Data Source
AI summary
An address controller includes a bit selector that receives a first portion of a requester id and selects a bit from a vector that identifies whether a requesting function is an SR-IOV device or a standard PCIe device. The controller also includes a selector coupled to the bit selector that forms an output comprised of either a second portion of the RID or a first portion of the address portion based on an input received from the selector and an address control unit that receives the first portion of the RID and the output and determines the LPAR that owns the requesting function based thereon, the address control unit providing the corrected memory request to the memory.