PCIe Address Bits Convey Platform Hints for Data Transaction Optimization

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Many devices do not support optional fields like Steering Tag, Relaxed Ordering, and Last Level Cache in PCIe protocols, leading to sub-optimal performance in data transactions.

Innovation Solution

Exploiting unused address bits to convey platform hints and attributes, allowing devices to use these optional features even if they are not natively supported, by configuring device drivers to populate these hints in address bits and using them to optimize data transfers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If optional fields (ST, RO, LLC, stashing field) are used in PCIe protocol, then data transaction performance is improved, but device compatibility is reduced because many devices do not support these optional fields

Engineering Contradiction:
Improvedata transaction performanceVSAvoiddevice compatibility
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent introduces an intermediary mechanism where the system side acts as a mediator between devices that support optional fields and devices that do not. The system side receives platform hints from supporting devices and translates them into address bit modifications that non-supporting devices can understand, enabling performance optimization without requiring all devices to support the optional fields natively

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the parameter representation by mapping optional field values to address bit patterns. Instead of using dedicated optional fields that must be supported by all devices, the system encodes platform hints as specific address bit configurations that can be interpreted by both supporting and non-supporting devices, thereby maintaining compatibility while enabling performance optimization

Inventive Principle:
Principle #35Parameter changes

2Productivity

If platform hints are conveyed through optional fields, then data transfer optimization is improved, but system complexity increases due to the need to handle both supporting and non-supporting devices

Engineering Contradiction:
Improvedata transfer optimizationVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent extracts the platform hint functionality from the optional fields and relocates it to the address bit space. By taking out the hint mechanism from the dedicated optional fields and embedding it in the address bits, the system simplifies the overall architecture because address bits are already universally handled by all devices, eliminating the need for separate hint handling paths

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent makes the address bits multi-functional by using them both for traditional addressing purposes and for conveying platform hints. This universal usage of address bits eliminates the need for separate hint transmission mechanisms, reducing system complexity while maintaining optimization capabilities for both supporting and non-supporting devices

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11762785B2Peripheral component interconnect attributes shared using address bits
Publication Date: 2023.09.19 MELLANOX TECHNOLOGIES LTD(IL)
  • US11762785B2 patent drawing
  • US11762785B2 patent drawing
  • US11762785B2 patent drawing

AI summary

A system and method are provided. In one example, a system is disclosed that includes a memory device and a first interface configured to connect with a first external device. The interface may include a device side that enables a first data exchange with the first external device and a system side that enables a second data exchange with the memory device, where the system side further enables an exchange of platform hints between the first interface and the memory device. The system may also include a hinting unit that populates the platform hints in an address bit.