PCIe ATS Fast Invalidation via Batch Processing

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Solution Overview

Problem

The existing address translation invalidation process in PCIe systems is inefficient, leading to signaling overhead and latency due to the need for immediate acknowledgement and processing of invalidation commands by peripherals.

Innovation Solution

Implementing a fast invalidation request mechanism that allows endpoints to accumulate invalidation requests until a synchronization command is sent, along with the use of tags with incrementing identifiers to detect missing or corrupted messages, thereby reducing overhead and ensuring complete processing of invalidation commands.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If immediate acknowledgement and processing of invalidation commands is required, then reliability of address translation is improved, but signaling overhead and latency increase

Engineering Contradiction:
Improveaddress translation reliabilityVSAvoidsignaling overhead
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The host sends invalidation requests in advance before the peripheral needs to use the address, allowing the peripheral to accumulate and process these requests together. This preliminary action reduces the need for immediate responses and lowers signaling overhead while maintaining reliability through batch processing.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Multiple invalidation requests are merged into a single batch processing operation. Instead of handling each invalidation request individually with immediate acknowledgement, the peripheral accumulates multiple requests and processes them together in one operation, reducing the total number of signaling exchanges.

Inventive Principle:
Principle #5Merging (Combining)

2Measurement precision

If immediate acknowledgement of invalidation commands is enforced, then address translation accuracy is improved, but processing time and latency increase

Engineering Contradiction:
Improveaddress translation accuracyVSAvoidprocessing latency
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

Invalidation requests are prepared and sent in advance, allowing the peripheral to accumulate them before actual address translation is needed. This preliminary preparation eliminates the need for immediate processing and acknowledgement, reducing latency while maintaining accuracy through batch validation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system uses periodic synchronization commands to trigger batch processing of accumulated invalidation requests. Instead of continuous immediate processing, the system processes invalidations in periodic batches, reducing overall processing time and latency while maintaining translation accuracy.

Inventive Principle:
Principle #19Periodic action

3Reliability

If multiple invalidation commands are processed individually, then reliability of address invalidation is improved, but device complexity and signaling overhead increase

Engineering Contradiction:
Improveinvalidation reliabilityVSAvoidinvalidation processing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Multiple individual invalidation commands are merged into a single batch processing operation. The peripheral maintains a queue of invalidation requests and processes them together in one operation, reducing the complexity of handling multiple separate commands while maintaining reliability through comprehensive batch invalidation.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The system introduces a synchronization mechanism as an intermediary between the host and peripheral. This mediator coordinates the batch processing of invalidation requests, ensuring all requests are properly handled without requiring the peripheral to manage multiple individual invalidation commands simultaneously, thus reducing processing complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP3735637B1Fast invalidation in peripheral component interconnect (PCI) express (PCIE) address translation services (ATS)
Publication Date: 2025.05.14 QUALCOMM INC
  • EP3735637B1 patent drawingFigure 1
  • EP3735637B1 patent drawingFigure 2
  • EP3735637B1 patent drawingFigure 3

AI summary

Fast invalidation in peripheral component interconnect (PCI) express (PCIe) address translation services (ATS) initially utilize a fast invalidation request to alert endpoints that an address is being invalidated with a fast invalidation synchronization command that causes the endpoints to flush through any residual read/write commands associated with any invalidated address and delete any associated address entries in an address translation cache (ATC). Each endpoint may send a synchronization complete acknowledgement to the host. Further, a tag having an incrementing identifier for each invalidation request may be used to determine if an endpoint has missed an invalidation request.