Storage Block Transfer With Concurrent Error Control Over PCIe
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Solution Overview
Problem
Current interfaces in computer systems, such as SATA, limit data transfer rates due to latency and overhead from error detection and correction, which restrict the throughput between high-speed storage devices and hosts.
Innovation Solution
A system that transfers data from a storage device to a host using a PCIe interface, performing error detection and correction concurrently, allowing out-of-order retransmission of blocks once errors are corrected, thereby reducing latency and increasing bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detection and correction are performed before data transmission over SATA interface, then data reliability is improved, but transmission latency increases and throughput decreases
Solution Approach 1:
The patent performs error detection and correction in advance on the host side before data is transferred to the storage device. By pre-processing error control on the host rather than during transmission, the system ensures data reliability while minimizing transmission latency, as the error control operations do not block the data transfer path.
Solution Approach 2:
The patent introduces a buffer memory as an intermediary between the host and storage device. The buffer temporarily holds data during transfer, allowing error detection and correction operations to be performed asynchronously without blocking the main data transfer path, thus reducing transmission latency while maintaining reliability.
2Reliability
If error detection and correction are performed before data transmission, then data reliability is improved, but effective throughput decreases due to overhead
Solution Approach 1:
The patent performs error detection and correction before data transmission on the host side, allowing these operations to be optimized and batched without affecting the storage device's transmission capacity. This preliminary processing improves reliability while minimizing the impact on effective throughput by not adding overhead during the actual data transfer.
Solution Approach 2:
The host system performs error detection and correction on its own behalf before transmitting data, eliminating the need for the storage device to perform these operations during reception. This self-service approach reduces the overall system overhead and improves effective throughput by distributing the error control burden to the host's processing capabilities.
3Adaptability or versatility
If traditional SATA interface with 8b/10b encoding is used, then compatibility is maintained, but data transfer rate is limited and throughput decreases
Solution Approach 1:
The patent changes the interface parameters by using PCIe with NVLink instead of traditional SATA with 8b/10b encoding. This parameter change enables higher data transfer rates (up to 32 GB/s compared to SATA's 6 Gbits/s) while maintaining adaptability through the PCIe standard's widespread support and configurability in modern computer systems.
Solution Approach 2:
The patent inverts the traditional approach by making the host the active initiator of error control operations rather than the storage device. This inversion, combined with using PCIe/NVLink instead of SATA, allows the system to achieve higher throughput by leveraging the host's processing power and the faster interface, while maintaining compatibility through standard PCIe protocols.
Data Source
AI summary
The disclosed embodiments provide a system that transfers data from a storage device to a host. The system includes a communication mechanism that receives a request to read a set of blocks from the host. Next, upon reading each block from the set of blocks from the storage device, the communication mechanism transfers the block over an interface with the host. The system also includes an error-detection apparatus that performs error detection on the block upon reading the block, and an error-correction apparatus that performs error correction on the block if an error is detected in the block. The communication mechanism may then retransfer the block to the host after the error is removed from the block.