PCIe Bridge Address Translation for Scalable Multi-Chip Daisy Chains

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Solution Overview

Problem

Existing computing systems face challenges in efficiently managing communication between multiple chips using Peripheral Component Interconnect Express (PCIe) due to the need for complex software intervention and address translation for multi-function endpoints, limiting compatibility and scalability.

Innovation Solution

A system-on-chip (SoC) with a multi-function endpoint controller and a centralized transaction tunneling unit that eliminates the need for software intervention, enabling secure and scalable communication paths between multiple chips through PCIe by integrating a multi-chip daisy chain topology.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If complex software intervention and address translation are used for multi-function endpoints, then communication between multiple chips is enabled, but system complexity and configuration difficulty increase

Engineering Contradiction:

Improvemulti-chip communication capabilityVSAvoidsoftware intervention complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent introduces a PCIe bridge device as an intermediary component between the host and multiple endpoint devices. This bridge handles address translation and transaction routing automatically, eliminating the need for complex software intervention. The bridge receives transactions from the host, translates addresses according to configured mappings, and forwards transactions to the appropriate endpoint devices in the daisy-chain topology.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The system enables self-service by allowing the PCIe bridge to automatically perform address translation and transaction routing without external software control. The bridge is configured with address mapping tables that enable it to autonomously determine the destination of each transaction and perform the necessary address translation, making the system self-configuring and reducing software complexity.

Inventive Principle:

Principle #25Self-service

2Reliability

If custom configuration is required for each chip connection, then communication paths can be established, but scalability and compatibility are limited

Engineering Contradiction:

Improvecommunication path establishmentVSAvoidscalability and compatibility

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The PCIe bridge is designed with universal functionality to support multiple endpoint devices with different functions (graphics processing, AI processing, storage, etc.) in a standardized daisy-chain topology. The bridge implements a unified address translation mechanism that works with various endpoint types, enabling scalable system expansion without requiring custom configuration for each device combination.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system uses configurable address mapping parameters in the PCIe bridge to adapt to different system configurations. By changing the address translation tables and routing parameters in the bridge, the same hardware topology can support different numbers and types of endpoint devices, enabling scalability and compatibility across various configurations without hardware changes.

Inventive Principle:

Principle #35Parameter changes

3Adaptability or versatility

If address translation is performed for each transaction, then multi-function endpoint communication is enabled, but transaction processing time increases

Engineering Contradiction:

Improvemulti-function endpoint supportVSAvoidtransaction processing time

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The PCIe bridge performs preliminary address translation by pre-configuring address mapping tables during system initialization. Common address translations are pre-computed and stored in the bridge's translation tables, allowing the bridge to perform quick table-lookup-based translation for subsequent transactions rather than performing complex translation algorithms for each transaction, thus reducing processing time.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system uses address mapping table copies stored in the PCIe bridge to enable fast translation. Instead of performing full address translation calculations for each transaction, the bridge maintains copied address mapping information in its translation tables, allowing rapid comparison and translation decision-making based on pre-stored mapping data.

Inventive Principle:

Principle #26Copying

Data Source

PatentUS12411795B2Enabling a multi-chip daisy chain topology using peripheral component interconnect express (PCIe)

Publication Date: 2025.09.09 TEXAS INSTRUMENTS INC

AI summary

A system-on-chip (SoC) may be configured to enable a Multi-Chip Daisy Chain Topology using peripheral component interface express (PCIe). The SoC may include a processor, a local memory, a root complex operably connected to the processor and the local memory, and a multi-function endpoint controller. The root complex may obtain forwarding information to configure routing of transactions to one or more PCIe endpoint functions or to the local memory. The root complex may initialize, based on the forwarding information, access between a host and the one or more PCIe endpoint functions. The multi-function endpoint controller may obtain a descriptor and endpoint information to configure outbound portals for transactions to at least one remote host. The multi-function endpoint controller may establish a communication path between the host and a function out of a plurality of functions.