PCIe Bus Latency Measurement Using Reference Clock Synchronization
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Solution Overview
Problem
Accurately measuring latency between a field programmable gate array (FPGA) and a conventional processor (CPU) connected by a PCI Express (PCIe) bus is challenging due to clock drift and synchronization issues, especially in systems where each component has its own independent timing.
Innovation Solution
A method and system that utilize a PCIe reference clock to synchronize the FPGA and CPU clocks, allowing for the conversion of FPGA clock ticks to CPU Time Stamp Counter (TSC) ticks using a calibration offset, thereby eliminating drift and enabling precise latency measurement across the PCIe bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If independent counters are used in FPGA and CPU for timing measurements, then each component can measure time independently, but clock drift causes synchronization errors and reduces measurement accuracy
Solution Approach 1:
The patent introduces a PCIe reference clock as an intermediary that both FPGA and CPU use for timing measurements. This mediator synchronizes the independent counters by providing a common time reference, eliminating clock drift issues while preserving independent measurement capabilities.
Solution Approach 2:
The patent changes the timing parameter from using independent component clocks to using a shared PCIe reference clock frequency. By standardizing the time base frequency across both FPGA and CPU, the system maintains independent operation while achieving synchronization for accurate latency measurement.
2Measurement precision
If separate calibration procedures are implemented for FPGA and CPU counters, then initial synchronization can be achieved, but ongoing drift requires continuous recalibration increasing system complexity
Solution Approach 1:
The patent performs calibration once during system initialization by comparing the FPGA counter and CPU TSC values, then calculates a conversion factor. This preliminary action establishes a stable relationship between the two counters that remains valid throughout operation, eliminating the need for continuous recalibration.
Solution Approach 2:
The patent creates a virtual copy of the PCIe reference clock timing in both FPGA and CPU, allowing one to simulate or model the behavior of the other. By copying the time reference relationship and applying a conversion factor, the system maintains synchronization without complex ongoing calibration.
3Speed
If different incrementation rates are used by FPGA and CPU counters, then each component can operate at its optimal clock frequency, but conversion between time measurements becomes complex and error-prone
Solution Approach 1:
The patent changes the approach from direct one-to-one counter matching to a scaled relationship. By introducing a conversion factor that represents the ratio between PCIe reference clock frequency and CPU TSC frequency, the system allows different operating speeds while maintaining a simple linear relationship for time conversion.
Data Source
AI summary
Methods and systems for determining latency across a bus, such as a PCIe bus, coupling a field programmable gate array (FPGA) and a processor having different time incrementation rates. Both the FPGA and the processor count clock ticks independently, and using a calibration offset and the two incrementation rates, the processor converts the FPGA clock ticks into processor clock ticks in order to determine latency across the bus.