PCIe Bus Partial Fallback for Error Isolation
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Solution Overview
Problem
In storage devices with PCIe buses, frequent correctable errors can lead to system performance degradation and require fallback processing, which may result in communication unavailability and business disruption due to the need to isolate malfunctioning controller modules.
Innovation Solution
A storage device with a detector for correctable errors and a connection controller that performs partial fallback processing by reducing link speed or isolating lanes of the PCIe bus when error thresholds are exceeded, maintaining communication without shutting down the system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fallback processing is carried out to handle frequent correctable errors, then system reliability is improved, but communication unavailability increases and business disruption occurs
Solution Approach 1:
The PCIe bus is segmented into multiple independent lanes. When errors are detected in specific lanes, only those problematic lanes are isolated through fallback processing, while other healthy lanes continue to operate. This segmentation allows the system to maintain communication functionality through remaining lanes, preventing complete communication unavailability while still handling errors reliably.
2Reliability
If complete fallback processing is implemented to isolate malfunctioning controller modules, then error handling is improved, but system performance degradation occurs due to communication shutdown
Solution Approach 1:
Instead of implementing complete fallback processing that shuts down entire controller modules, the system applies partial fallback processing that isolates only the specific problematic lanes within the PCIe bus. This partial action approach handles errors effectively while preserving the functionality of other lanes, thereby maintaining system performance and avoiding unnecessary communication shutdowns.
3Stability of the object's composition
If PCIe bus lanes are isolated to correct errors, then communication stability is improved, but data transmission capacity decreases
Solution Approach 1:
The PCIe bus is divided into multiple independent lanes that can be individually managed. When errors occur, only the affected lanes are isolated while other lanes continue to transmit data. This segmentation strategy maintains communication stability by removing error sources while preserving data transmission capacity through the remaining functional lanes, avoiding the need to reduce capacity across the entire bus.
Data Source
AI summary
A storage device, includes: a plurality of controller modules; a bus disposed among the plurality of controller modules, the bus including a plurality of transmission paths; a detector configured to detect an error in data communication through the bus; and a connection controller configured to carry out partial fallback processing of the bus if the number of the errors has exceeded a given number.