PCIe Bus Topology Using Passive Selector Circuits
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Solution Overview
Problem
The existing high-speed serial computer expansion bus standards, such as PCIExpress, face issues with signal reflection and increased cost, power consumption, and space wastage due to the need for PCIE switching chips when multiplexing channels, especially in systems with varying configurations.
Innovation Solution
A high-speed serial computer expansion bus circuit topology that uses resistor and capacitor superposition layouts to minimize signal reflection and eliminate the need for PCIE switching chips by employing selector circuits with passive elements, allowing for efficient multiplexing of PCIE GEN3 channels without the need for additional hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If PCIE switching chips are used to multiplex channels, then channel multiplexing capability is improved, but device complexity, cost, and power consumption increase
Solution Approach 1:
The patent extracts the switching function from a dedicated PCIE switching chip and implements it using passive elements (resistors and capacitors) integrated into the circuit topology. This removes the need for complex active switching components while retaining channel multiplexing capability through selective signal path routing.
Solution Approach 2:
The patent creates a simplified version of the switching function by using passive element networks that replicate the channel selection capability of active switching chips. The resistor-capacitor networks copy the essential routing function without requiring complex control logic or active components.
2Adaptability or versatility
If PCIE switching chips are used to multiplex channels, then channel multiplexing capability is improved, but cost increases
Solution Approach 1:
The patent replaces expensive PCIE switching chips with inexpensive passive elements (resistors and capacitors) that can be easily manufactured and integrated into the circuit board. These passive components are significantly cheaper than active switching chips while providing the necessary channel selection functionality.
Solution Approach 2:
The patent substitutes the electronic switching mechanism (using active components and control logic) with a passive electrical network based on resistor-capacitor combinations. This substitution eliminates the need for complex control circuits and reduces manufacturing costs.
3Adaptability or versatility
If PCIE switching chips are used to multiplex channels, then channel multiplexing capability is improved, but power consumption increases
Solution Approach 1:
The patent implements a self-service switching mechanism where the passive element networks automatically route signals based on their electrical characteristics without requiring external control signals or power consumption for switching operations. The circuit topology itself performs the channel selection function passively.
Solution Approach 2:
The patent replaces the active electronic switching system (which requires power for control logic and signal routing) with a passive electrical network that performs channel multiplexing without consuming power for the switching operation itself.
4Adaptability or versatility
If PCIE switching chips are used to multiplex channels, then channel multiplexing capability is improved, but board space increases
Solution Approach 1:
The patent merges the switching function with the existing circuit board layout by integrating passive elements directly into the signal paths. Instead of adding a separate switching chip that occupies additional board space, the channel multiplexing functionality is combined with the existing PCB trace routing and component placement.
Solution Approach 2:
The passive element networks serve multiple functions: they provide channel multiplexing capability while also functioning as part of the signal transmission path and impedance matching network. This multi-functionality eliminates the need for dedicated switching chip real estate on the board.
Data Source
AI summary
A high-speed serial computer expansion bus circuit topology, comprises: a first signal path connecting between a first interface and a second interface, a second signal path connecting between the first interface and a third interface, a third signal path connecting between the third interface and a fourth interface, a first selector circuit having a first passive element and a second passive element which are respectively disposed in the first signal path and the second signal path, a second selector circuit having a third passive element and a fourth passive element which are respectively disposed in the second signal path and the third signal path. The second signal path is conducted when the first passive element and the second passive element are conducted, the third signal path is conducted when the third passive element and the fourth passive element are conducted.