PCIe Cache Coherency via Snoop Request and Complete Message
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Solution Overview
Problem
In conventional computing systems, data marked as "uncacheable" (UC) or "write-combining" (WC) cannot be cached across a PCIe bus, leading to significant latency and reduced processor efficiency due to the inability to maintain cache coherency, which limits system configurations.
Innovation Solution
A method and system that utilize a snoop request and complete message to determine cache coherency across processors connected by a PCIe bus, allowing data to be marked as "cacheable" and enabling processors to execute operations without serializing instructions, thereby improving processor speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is marked as uncacheable (UC) or write-combining (WC) across PCIe bus, then cache coherency is maintained, but processor performance deteriorates due to significant latency and inability to cache data
Solution Approach 1:
The patent changes the cacheability parameter of data transmitted across PCIe bus from UC/WC to cacheable by implementing a snoop request mechanism that actively maintains cache coherency, allowing data to be cached while preserving reliability through coherence protocols
Solution Approach 2:
The snoop request acts as an intermediary mechanism between processors across the PCIe bus, enabling cache coherency monitoring and maintenance that allows cacheable data marking while preventing coherency violations
2Reliability
If data is marked as uncacheable (UC) across PCIe bus, then cache coherency is maintained, but execution efficiency deteriorates due to instruction serialization
Solution Approach 1:
The patent changes the cacheability parameter from UC to cacheable, which removes the requirement for instruction serialization and allows parallel execution while maintaining coherency through the snoop request mechanism
3Productivity
If data is cached across PCIe bus without snoop mechanism, then processor performance improves, but cache coherency deteriorates due to inability to maintain consistency
Solution Approach 1:
The snoop request serves as an intermediary that enables caching while maintaining coherency by monitoring and validating cache states across processors, allowing performance improvement without sacrificing reliability
Data Source
AI summary
Techniques are disclosed for maintaining cache coherency across a serial interface bus such as a Peripheral Component Interconnect Express (PCIe) bus. The techniques include generating a snoop request (SNP) to determine whether first data stored in a local memory is coherent relative to second data stored in a data cache, the snoop request including destination information that identifies the data cache on the serial interface bus and causing the snoop request to be transmitted over the serial interface bus to a second processor. The techniques further include extracting a cache line address from the snoop request, determining whether the second data is coherent, generating a complete message (CPL) indicating that the first data is coherent with the second data, and causing the complete message to be transmitted over the bus to the first processor. The snoop request and complete messages may be vendor defined messages.