PCIe Clock Phase Adjustment for Server Mainboard Data Reliability
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Solution Overview
Problem
The reliability of communication between a server mainboard and a PCIe expansion board is compromised due to time costs during data transmission, as data transmitted by the initiating end may not reach the receiving end at the next high-level moment, making it challenging to ensure consistent data exchange.
Innovation Solution
A clock control method that calculates hardware parameters to determine time margins for data transmission, generates a clock phase difference based on these margins, and adjusts clock signals to synchronize data transmission and reception, ensuring reliable bidirectional communication by optimizing timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data transmission is performed at the next high-level moment of the clock signal, then communication speed is maintained, but data reliability deteriorates because transmitted data may not reach the receiving end in time
Solution Approach 1:
The patent calculates time margins (first time margin and second time margin) based on hardware parameters before initiating data transmission. By determining the clock phase difference in advance and adjusting clock signals accordingly, the system ensures that data will arrive at the receiving end before the next high-level moment, thus maintaining both high communication speed and reliable data transmission.
2Device complexity
If clock signals are synchronized without phase adjustment, then system complexity is reduced, but communication reliability deteriorates due to transmission delays
Solution Approach 1:
The patent introduces a clock phase difference parameter derived from calculated time margins. By adjusting the phase of clock signals based on this parameter, the system compensates for transmission delays without requiring complex control mechanisms. This parameter-based approach maintains communication reliability while keeping the control system relatively simple.
3Reliability
If time margins are increased to ensure data arrival, then communication reliability improves, but transmission efficiency deteriorates due to longer timing windows
Solution Approach 1:
The patent applies different time margin requirements to different transmission directions (first time margin for one direction, second time margin for the other direction). By calculating and applying direction-specific time margins rather than a uniform margin, the system ensures reliable data arrival while minimizing the timing window extension, thus maintaining transmission efficiency.
Data Source
AI summary
A clock control method, apparatus, and device, and a storage medium. By the method, timing optimization of bidirectional data communication between a server mainboard and a Peripheral Component Interconnect express (PCIe) expansion board is relatively implemented, and the occurrence of a situation where in any data communication direction between the server mainboard and the PCIe expansion board, data transmitted by the initiating end at a given high-level moment does not reach the receiving end at a next high-level moment may be prevented, thus ensuring the reliability of communication between the server mainboard and the PCIe expansion board. In addition, the present application further provides a clock control apparatus and device, and a storage medium, and the beneficial effects are as stated above.