PCIe Clock Synchronization Using PPM Correction and SSC Matching
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Solution Overview
Problem
Achieving precise clocking synchronization between PCIe host and endpoint communication nodes while minimizing Electro Magnetic Interference (EMI) and Radio Frequency Interference (RFI) is challenging due to the requirement for a common reference clock with tight skew specifications, which often results in increased latency, power consumption, and die area when using elastic buffers and servo phase-locking mechanisms.
Innovation Solution
The endpoint communication node synchronizes its clock with the host node during clock training by performing static phase measurement and applying parts-per-million (PPM) correction, and continuously monitors and adjusts its spread spectrum clocking (SSC) pattern to match the host's SSC pattern, using methods such as detecting 0 PPM events, message-based approaches, or master phase lock loop signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If elastic buffers with large buffer depth are added to compensate for skew, then clock skew tolerance is improved, but latency and die area increase
Solution Approach 1:
The patent extracts and removes the elastic buffer component from the system by implementing a digital skew compensation mechanism that calculates and corrects skew through signal processing rather than physical buffering, thereby eliminating the latency and area overhead associated with large buffer depths
Solution Approach 2:
The patent replaces the mechanical elastic buffer system with a digital signal processing approach that uses skew detection and compensation algorithms to achieve the same skew tolerance function without the physical constraints of buffer depth, latency, and area
2Manufacturing precision
If elastic buffers with large buffer depth are added to compensate for skew, then clock skew tolerance is improved, but die area increases
Solution Approach 1:
The patent extracts and removes the elastic buffer component from the system by implementing a digital skew compensation mechanism that calculates and corrects skew through signal processing rather than physical buffering, thereby eliminating the area overhead associated with large buffer depths
Solution Approach 2:
The patent replaces the mechanical elastic buffer system with a digital signal processing approach that uses skew detection and compensation algorithms to achieve the same skew tolerance function without the physical constraints of buffer depth and area
3Reliability
If servo phase-locking mechanism with common Refclk is used, then clock synchronization is improved, but power consumption increases
Solution Approach 1:
The patent extracts and removes the power-consuming servo phase-locking mechanism by implementing a digital skew compensation approach that achieves synchronization through calculation and correction rather than continuous active control, thereby reducing power consumption while maintaining synchronization reliability
Data Source
AI summary
Method and apparatus associated with clocking synchronization are disclosed herein. In various embodiment, a method for communication comprises: entering a clock training period, on successful performance of clock training handshake; entering a start static phase measurement (SSPM) sequence of clock training period, receiving a recovered clock; and processing the recovered clock to determine parts-per-million (PPM) differences, to be subsequently applied to compensate for the PPM differences determined during subsequent clocking synchronization. Linking training is performed after the subsequent clocking synchronization. In various embodiments, clocking synchronization comprises SSC synchronization. Other embodiments are also described and claimed.