PCIe Interface Device Clock Switching for Link Recovery
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Solution Overview
Problem
PCIe interface devices face challenges in link recovery performance, particularly in managing clock transitions and data processing during reset signals and reference clock fluctuations, which can lead to inefficiencies and potential system failures.
Innovation Solution
A PCIe interface device with a PCIe protocol stack and a controller that switches the operating clock from a PCIe clock to an internal clock based on reset signals and reference clock conditions, enabling effective data flushing and transaction processing, and initiating link recovery operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the operating clock is switched from PCIe clock to internal clock during reset or reference clock failure, then link recovery performance is improved, but device complexity increases
Solution Approach 1:
The system performs preliminary actions by switching to the internal clock before the reference clock fully fails or during reset assertion. This proactive clock switching ensures that the PCIe protocol stack can continue processing data and maintain link recovery operations without interruption, resolving the contradiction by preparing the system in advance rather than reacting after failure occurs.
Solution Approach 2:
The internal clock serves as an intermediary between the failed reference clock and the PCIe protocol stack. When the reference clock is off or reset is asserted, the internal clock mediates by providing continuous clock signals to maintain data processing and link recovery functions, thus improving reliability while isolating the complexity of clock management within a specific component.
2Reliability
If data flushing is performed based on internal clock during clock transitions, then data processing reliability is improved, but loss of time occurs
Solution Approach 1:
The system maintains continuity of useful action by performing data flushing operations based on the internal clock during transitions from PCIe clock to internal clock. This ensures that data processing continues without interruption or gaps, maintaining reliability while minimizing time loss by keeping the flushing operation synchronized with the available clock signal throughout the transition period.
3Reliability
If link recovery operations are initiated during reset or reference clock failure, then system reliability is improved, but productivity decreases
Solution Approach 1:
The system applies dynamics by adaptively adjusting its operation mode based on clock availability. When reference clock is off or reset is asserted, the system dynamically switches to using internal clock for link recovery operations. This dynamic adaptation allows the system to maintain reliability under failure conditions while automatically returning to normal high-productivity mode when the reference clock is restored, thus resolving the contradiction between reliability and productivity.
Data Source
AI summary
A Peripheral Component Interconnect Express (PCIe) interface device includes a PCIe layer and a PCIe controller. The PCIe layer performs communication between a host and a Direct Memory Access (DMA) device. The PCIe controller switches an operating clock from a PCIe clock generated based on a reference clock to an internal clock, processes data of the PCIe layer on the basis of the internal clock, and recovers a link with respect to the host, when a reset signal received from the host is asserted or the reference clock is off.