PCIe Clock Synchronization Using TLP Prefixes
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Solution Overview
Problem
Current precision time measurement (PTM) techniques for clock synchronization in PCI Express (PCIe) links are limited by requiring the master clock to be behind the downstream port, which restricts topology flexibility and increases signaling overhead, making them undesirable for certain configurations like application processor-to-modem links.
Innovation Solution
The proposed solution involves positioning the master clock at either the downstream-facing or upstream-facing port and using Transport Layer Protocol (TLP) prefixes to send synchronization commands with timestamps, allowing the slave clock to update its time value and calculate round trip delays, thereby reducing signaling overhead and enabling synchronization from either port.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If precision time measurement (PTM) techniques are used for clock synchronization, then clock synchronization is achieved, but the master clock must be positioned behind the downstream port which restricts topology flexibility and increases signaling overhead
Solution Approach 1:
The patent inverts the traditional PTM approach by allowing the master clock to be positioned at the upstream port instead of the downstream port. This is achieved by reversing the direction of synchronization commands and timestamps, enabling the upstream device to send synchronization information to the downstream device, thereby achieving clock synchronization while providing topology flexibility.
Solution Approach 2:
The patent makes the synchronization mechanism universal by enabling it to work in both traditional PTM configurations and the new upstream-master configurations. The same TLP prefix mechanism and timestamp comparison logic are used regardless of which device holds the master clock, allowing the system to adapt to different topologies without requiring separate synchronization protocols.
2Reliability
If precision time measurement (PTM) techniques are used for clock synchronization, then clock synchronization is achieved, but signaling overhead increases
Solution Approach 1:
The patent merges the clock synchronization function with the existing TLP (Transport Layer Packet) data transmission mechanism. By embedding synchronization timestamps and commands within the TLP prefixes that are already being exchanged for data transmission, the patent eliminates the need for separate dedicated synchronization signaling, thereby reducing overall signaling overhead while maintaining synchronization reliability.
3Adaptability or versatility
If master clock is positioned at upstream port, then topology flexibility is improved, but traditional PTM techniques become inapplicable
Solution Approach 1:
The patent creates a universal synchronization mechanism that works regardless of which port holds the master clock. The same TLP prefix structure, timestamp generation, and time value comparison logic are used whether the master is at the downstream port (traditional PTM) or upstream port (new approach), simplifying implementation by eliminating the need for separate handling of different topologies.
Data Source
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AI summary
Systems and methods for time synchronization for clocks separated by a communication link allow a master clock to be positioned at a downstream-facing port or an upstream-facing port and to send synchronization commands with an associated time stamp embedded in transport layer protocol (TLP) prefixes to a slave clock. The slave clock may update its time value based on the received time stamp. Further, the slave may calculate a round trip delay between the master clock and the slave clock and use this delay calculation to correct the slave clock. The delay calculation may likewise be made using TLP prefixes. By using TLP prefixes in this fashion, the time synchronization can piggyback on existing message traffic, which reduces signaling overhead. Likewise, by using the TLP prefixes, the time synchronization may be initiated from either an upstream-facing port or a downstream-facing port.