PCIe Command Prefetch and Dynamic Power Management

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current PCIe systems face inefficiencies in command fetching and power management, leading to increased latency and power consumption, particularly during idle states, as they rely on traditional methods that do not effectively detect and respond to idle link conditions.

Innovation Solution

The implementation of a PCIe system and method that registers a lightweight notification (LN) and prefetches commands, along with advanced power management techniques that detect idle states and dynamically change power modes to reduce power consumption, such as transitioning to lower power states like L1 and L1.2 when no commands are being processed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If traditional PCIe command fetching methods are used, then the system maintains simple operation, but command fetching time increases and system productivity decreases

Engineering Contradiction:
Improvecommand fetching timeVSAvoidsystem complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent implements command prefetching by having the PCIe device proactively fetch commands from host memory before they are actually needed for execution. The device monitors the command queue and initiates prefetch operations when the queue is empty or has few commands, thereby reducing idle waiting time and improving command fetching efficiency without requiring fundamental changes to the PCIe protocol

Inventive Principle:
Principle #10Preliminary action

2Speed

If the PCIe link remains in active state to ensure quick command response, then command fetching speed is maintained, but power consumption increases during idle periods

Engineering Contradiction:
Improvecommand response speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic power management by transitioning the PCIe link between different power states (L0, L1, L1.2) based on actual workload conditions. The system monitors command queue status and link activity, dynamically adjusting the link state to balance between power savings during idle periods and quick response capability when commands are pending, thereby resolving the contradiction between speed and power consumption

Inventive Principle:
Principle #15Dynamics

3Use of energy by moving object

If the PCIe link transitions to low power states during idle periods, then power consumption is reduced, but latency increases when transitioning back to active state

Engineering Contradiction:
Improvepower consumptionVSAvoidlatency
Core Design Contradiction:
Use of energy by moving objectVSLoss of time

Solution Approach 1:

The patent reduces latency after power state transitions by implementing preliminary actions: keeping the command queue pre-filled with upcoming commands before transitioning to low power states, and maintaining buffer readiness in the PCIe device. This ensures that when the link wakes from L1/L1.2 states, commands are already available for immediate processing, minimizing the effective latency experienced by the system

Inventive Principle:
Principle #10Preliminary action

4Productivity

If lightweight notification (LN) registration is implemented to reduce command fetching time, then productivity improves, but device complexity increases

Engineering Contradiction:
Improvecommand processing efficiencyVSAvoidPCIe device complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent extracts and implements only the essential Lightweight Notification (LN) registration mechanism from the full PCIe notification framework, selectively enabling LN for command queue status notifications while maintaining other traditional notification methods for completion events. This selective extraction improves command processing efficiency through faster queue status awareness while avoiding the complexity overhead of implementing the entire PCIe notification suite

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS20220327074A1PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) SYSTEM AND METHOD OF OPERATING THE SAME
Publication Date: 2022.10.13 SK HYNIX INC
  • US20220327074A1 patent drawing
  • US20220327074A1 patent drawing
  • US20220327074A1 patent drawing

AI summary

The present technology relates to an electronic device. A computing system may include a host and a peripheral component interconnect express (PCIe) device connected the host through a link. The host comprises a host memory and a storage device driver. The host memory may store information on a first target command to be executed in the PCIe device. The storage device driver may provide the first target command to the host memory and a notification message indicating that the first target command is stored in the host memory to the PCIe device. The PCIe device may request the host memory to register an address of the host memory in which a second target command to be executed in the PCIe device is stored through a preset protocol.