PCIe Protocol Completion Status Encode for Processor Synchronization
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Solution Overview
Problem
Conventional PCIe interconnects are limited in processing complex commands, such as read-modify-write commands, which are necessary for synchronizing multiple processors, leading to inefficiencies in processor coordination and shared data access.
Innovation Solution
Modifying the PCIe protocol to include a completion status encode associated with synchronization commands, allowing for the recognition and processing of read-modify-write commands, and employing I/O bridge logic to perform data modification without transmitting data to the accelerator logic, thereby enabling efficient synchronization of processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the PCIe interconnect is used with conventional protocol, then the system maintains simplicity and compatibility, but it cannot process complex synchronization commands like read-modify-write operations
Solution Approach 1:
The synchronization command is segmented into multiple phases: a read phase where data is fetched from memory, a modify phase where the data is processed according to the synchronization operation, and a write phase where the modified data is returned to memory. This segmentation allows the PCIe interconnect to handle complex operations through a series of simpler, standardized transactions rather than requiring a single complex command protocol.
Solution Approach 2:
The system performs preliminary actions by pre-establishing the command structure and data paths before actual synchronization operations occur. The PCIe protocol is pre-configured with specific transaction types and completion status codes that enable synchronization operations, so that when a synchronization command is issued, the interconnect is already prepared to handle it through the predefined sequence of read-modify-write operations.
2Productivity
If data is transmitted to accelerator logic for modification, then processing can be distributed, but data transmission overhead increases
Solution Approach 1:
The invention extracts only the essential synchronization logic from the accelerator and places it in the PCIe interconnect itself. The interconnect reads data from memory, performs the modification locally using its own logic units, and writes the result back to memory without requiring the data to be transmitted to and from the accelerator. This extraction eliminates unnecessary data transmission while maintaining the productivity benefit of distributed processing.
Solution Approach 2:
The PCIe interconnect acts as an intermediary between the memory system and the accelerator logic. Instead of transmitting data between these components for synchronization operations, the interconnect mediates the operation by performing the read-modify-write sequence itself, using completion status codes to communicate the results back to the initiating processor. This intermediary role eliminates data transmission overhead while maintaining system productivity.
3Reliability
If the PCIe protocol is modified to include completion status encode, then synchronization commands can be properly recognized and processed, but the protocol becomes more complex
Solution Approach 1:
The completion status encode is implemented as a dynamic field within the existing PCIe protocol framework. Rather than creating a separate complex protocol, the status field adapts its meaning based on the type of transaction being completed. The same basic protocol structure handles both traditional read/write commands and new synchronization commands, with the completion status dynamically indicating the appropriate outcome state. This dynamic approach maintains reliability while minimizing protocol complexity.
Data Source
AI summary
In a first aspect, a first method of synchronizing a plurality of processors of a system is provided. The first method includes the steps of (1) modifying a peripheral component interconnect express (PCIe) protocol to include a completion status encode associated with a synchronization command that indicates whether a condition of the synchronization command is met; (2) providing a system including (a) a memory; (b) a first processor coupled to the memory; (c) a second processor; and (d) an interconnect coupling the second processor to the first processor and the memory; and (3) employing the modified PCIe protocol on the interconnect. Numerous other aspects are provided.