PCI-E Control Chip Port Selection Mechanism
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Solution Overview
Problem
A single PCI-E standard control chip cannot simultaneously arrange multiple upstream PCI-E standard ports, leading to increased manufacturing costs due to the need for multiple control chips to enable or disable these ports.
Innovation Solution
A PCI-E standard selection setting system and microserver that includes a System on Chip (SOC) with a PCI-E port, a PCI-E control chip generating selection signals, storage elements for arrangement settings, and a selection controller to generate multiple selection signals, allowing only one upstream PCI-E port to be arranged for data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single PCI-E standard control chip is used, then device complexity and manufacturing cost are reduced, but the capability to simultaneously arrange multiple upstream PCI-E standard ports is lost
Solution Approach 1:
The patent segments the port arrangement function by introducing a selection controller that receives a first selection signal and generates multiple second selection signals, each corresponding to a different storage element. This allows a single control chip to manage multiple upstream PCI-E ports by selectively activating different port arrangements through signal segmentation and distribution to multiple storage elements.
Solution Approach 2:
The patent introduces a selection controller as an intermediary component between the PCI-E control chip and multiple storage elements. This intermediary receives the first selection signal and generates multiple second selection signals that correspond to different storage elements, enabling the single control chip to indirectly manage multiple upstream ports through this mediating structure.
2Adaptability or versatility
If multiple PCI-E standard control chips are used to simultaneously enable or disable multiple upstream ports, then port arrangement capability is improved, but manufacturing cost increases
Solution Approach 1:
The patent makes the single PCI-E control chip universal by enabling it to arrange multiple different upstream PCI-E standard ports through the selection signal mechanism. The control chip can selectively activate different port configurations by generating multiple second selection signals that correspond to different storage elements, allowing one chip to perform the function previously requiring multiple chips.
Solution Approach 2:
The patent changes the operational parameters of the control chip by introducing a selection signal system that allows dynamic reconfiguration of which upstream port is arranged. By changing the state of the first selection signal and the corresponding second selection signals, the system can switch between different port arrangements without requiring physical hardware changes or multiple chips.
3Device complexity
If a single PCI-E control chip arranges only one upstream port at a time, then device simplicity is maintained, but operational flexibility and data transmission capability with multiple SOCs are reduced
Solution Approach 1:
The patent introduces dynamics into the previously static single-port arrangement system by implementing a selection signal mechanism that allows the control chip to dynamically switch between arranging different upstream PCI-E ports. The selection controller generates multiple second selection signals that can be activated in different states, enabling the system to adaptively configure which port is arranged based on operational requirements, thus providing dynamic reconfigurability.
Data Source
AI summary
A peripheral component interface-express (PCI-E) standard selection setting system and microserver are disclosed, in which a selection controller selects an arrangement setting in storage elements to arrange the PCI-E control chip, whereby each of the second PCI-E standard ports is or is not arranged as an upstream PCI-E standard port, so that a single PCI-E standard control chip may arrange one of the multitude of PCI-E standard ports as an upstream PCI-E standard port, so that the upstream PCI-E standard port may have a data transmission with one of the multitude of system on chips (SOCs) connected with the PCI-E standard control chip.