PCIe Controller Internal Loopback Path for Key Updates
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Solution Overview
Problem
Current PCIe protocols lack a method to establish an internal loopback data path, which is necessary for certain communication and key update operations within the PCIe controller without involving the host.
Innovation Solution
The implementation of a PCIe controller with internal loopback functionality, allowing for data transmission and key updates through a loopback path within the controller, replacing the host-end DMA transmission with storage space or DRAM, and enabling key updates without host intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If data is sent through the PCIe physical link for loopback, then the PCIe protocol loopback function is achieved, but the internal loopback data path cannot be established within the PCIe controller
Solution Approach 1:
The PCIe controller is segmented into distinct functional modules: a first PCIe controller, a second PCIe controller, and a memory module. Each module has specific responsibilities, with the first controller handling transmission and the second handling reception, allowing independent configuration of internal loopback paths without affecting the entire system.
Solution Approach 2:
The patent introduces an intermediary mechanism where the first PCIe controller's transmission module sends data to the second PCIe controller's reception module through an internal data path, rather than requiring external physical link traversal. This intermediary internal path enables loopback functionality while maintaining system complexity management.
2Productivity
If host intervention is required for key updates, then security management is simplified, but operational efficiency and security are reduced
Solution Approach 1:
The PCIe controllers are designed with self-service capability for key updates. The controllers can autonomously perform key update operations using their internal resources and communication paths, without requiring host system intervention. This is achieved through dedicated key management functionality integrated into the PCIe controllers themselves.
Solution Approach 2:
The system performs preliminary configuration of security keys and credentials within the PCIe controllers before actual data transmission or operations. This preliminary action includes establishing secure communication channels and configuring authentication mechanisms in advance, enabling automated key updates without host involvement during critical operations.
3Ease of operation
If DMA transmission uses external memory, then memory access flexibility is improved, but internal data path operations become more complex
Solution Approach 1:
The patent implements local quality by providing different memory access paths: an internal data path for operations requiring fast, direct access between PCIe controllers, and external memory paths for operations requiring broader memory access flexibility. The system selectively uses the appropriate path based on the specific operation requirements, optimizing both speed and flexibility.
Solution Approach 2:
The patent adds another dimension to the memory access architecture by introducing an internal data path dimension alongside the traditional external memory path. This creates a multi-dimensional access topology where data can flow through internal controllers directly or through external memory, providing flexibility in path selection without increasing the fundamental complexity of either path.
Data Source
AI summary
A PCIe controller and a loopback path using the PCIe controller. The PCIe controller includes: a transport layer transmission module, a transport layer reception module, a memory access module, and a memory, wherein the transport layer transmission module includes a first loopback control module, the transport layer reception module includes a second loopback control module, and the first loopback control module is coupled to the second loopback control module; the memory access module is coupled to the transport layer transmission module and the transport layer reception module, and the memory access module is also coupled to the memory.