PCIe Controller Swizzling for Flexible Motherboard Lane Routing
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Solution Overview
Problem
Conventional PCIe implementations impose limitations on how lanes can be routed on motherboards and how add-in-cards can be used, restricting flexibility in motherboard lane routing and down plugging configurations.
Innovation Solution
A PCIe controller performs arbitrary swizzling of lane ordering to comply with PCIe negotiation rules, using a full crossbar and arbitrary lane order negotiation logic to reorder lanes, allowing for greater freedom in motherboard lane routing and down plugging configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional PCIe implementations are used, then lane routing and add-in-card configurations are restricted by fixed rules, but this imposes limitations on motherboard design flexibility and down plugging options
Solution Approach 1:
The patent implements dynamic lane reordering capability where the PCIe controller can automatically adjust the physical-to-logical lane mapping based on the actual physical lane ordering detected during link training. This dynamic adaptation allows the system to handle arbitrary lane routings on the motherboard while maintaining compliance with PCIe negotiation rules, thereby improving routing flexibility without requiring complex manual configuration.
Solution Approach 2:
The invention changes the lane identification parameters by introducing a reordering mechanism that maps physical lane indices to logical lane indices through a configurable permutation. This parameter transformation allows the same physical lane infrastructure to support multiple different logical configurations, enabling flexible motherboard designs and down plugging options while maintaining protocol compliance.
2Adaptability or versatility
If arbitrary lane routing is implemented on motherboards, then routing flexibility is improved, but this may cause lane ordering conflicts with PCIe negotiation rules
Solution Approach 1:
The patent employs feedback mechanisms during the link training process where the controller detects the actual physical lane ordering and uses this information to automatically configure the appropriate reordering permutation. This feedback loop ensures that the lane mapping is dynamically adjusted to match the physical reality, guaranteeing successful PCIe negotiation while allowing arbitrary routing configurations.
Solution Approach 2:
The invention introduces an intermediary reordering layer between the physical lane infrastructure and the logical PCIe lane mapping. This intermediary mechanism acts as a translator that converts arbitrary physical lane orderings into compliant logical orderings, thereby mediating between routing flexibility requirements and protocol compliance requirements.
3Adaptability or versatility
If down plugging configurations are supported, then card compatibility is improved, but this restricts the available lane configurations and reduces flexibility
Solution Approach 1:
The patent segments the lane configuration management into independent units by implementing per-lane reordering control. This allows the system to independently manage and reorder individual lanes or groups of lanes, enabling flexible down plugging configurations where only the necessary lanes are activated while maintaining proper ordering. The segmentation reduces overall complexity by allowing modular configuration rather than requiring global reconfiguration.
Data Source
AI summary
A peripheral component interface express (PCIe) controller include a crossbar to reorder data lanes into an order compatible with PCIe negotiation rules. A full crossbar permits an arbitrary swizzling of data lanes, permitting greater flexibility in motherboard lane routing.