PCIe Controller Virtual Memory Address Decoupling

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Solution Overview

Problem

Device-side PCIe memory transactions cannot be unconditionally mapped to host memory due to the need for subtractive decoding, which degrades performance when all I/O transfers are buffered in the RAID controller.

Innovation Solution

A method and apparatus for mapping addresses in a host domain to a device domain using virtual memory with allocated virtual buffers and scatter/gather lists, allowing direct transfers between PCIe devices and host memory without fixed address mapping dependencies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If all I/O transfers are buffered in the RAID controller through double data rate memory, then device complexity is reduced, but performance degrades due to the necessity of subtractive decoding

Engineering Contradiction:

Improvecontroller complexityVSAvoiddata transfer performance

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The patent segments the address space into multiple regions, each region corresponding to a specific PCIe device. This segmentation eliminates the need for subtractive decoding by allowing the controller to directly route address-based transactions to the appropriate device or buffer, thereby maintaining performance while reducing complexity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces an address translation mechanism that acts as an intermediary between the host address space and device address spaces. This intermediary translates host addresses to device-specific addresses, enabling direct mapping without subtractive decoding and thus resolving the contradiction between simplified controller architecture and high data transfer performance.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Device complexity

If subtractive decoding is used to route PCIe transactions, then device complexity is reduced, but loss of time increases due to the decoding overhead

Engineering Contradiction:

Improverouting logic complexityVSAvoidtransaction routing time

Core Design Contradiction:

Device complexityVSLoss of time

Solution Approach 1:

The patent performs preliminary address translation and region mapping setup before actual data transactions occur. By pre-configuring the address-to-device mappings and establishing region descriptors in advance, the system eliminates the need for complex real-time subtractive decoding, thus reducing both controller complexity and transaction routing time.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS9858007B2Decoupling host and device address maps for a peripheral component interconnect express controller

Publication Date: 2018.01.02 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD

AI summary

A controller includes a virtual memory mapped to device-side Peripheral component interconnect express address space includes virtual buffers allocation for each data transfer. Each virtual buffer is associated with a scatter/gather list entry in a host memory. The controller executes direct transfers between Peripheral component interconnect express devices and host memory without introducing address mapping dependencies between the host and device domains.