PCIe-Based CPU Cluster Communication System

The patent extracts and removes Ethernet protocol overhead from the communication path by implementing direct PCIe-based communication between CPUs. The PCIe interface eliminates intermediate protocol processing layers, allowing raw data transmission without Ethernet framing, error checking, or flow control mechanisms, thereby achieving higher processing speeds while maintaining system compatibility through standard PCIe hardware.

The patent replaces the Ethernet protocol mechanism with a direct PCIe communication mechanism. Instead of using Ethernet's layered protocol stack (physical layer, data link layer, network layer), the system directly utilizes PCIe's simplified transaction protocol, substituting a complex mechanical protocol system with a more efficient direct hardware communication path that maintains compatibility through standard interfaces.

The patent employs standard PCIe interfaces and switches that are widely available, cost-effective components rather than expensive specialized high-speed network hardware. By using commodity PCIe technology that can be rapidly manufactured and deployed, the system achieves high-speed communication without the prohibitive costs of specialized network equipment, making the solution economically viable for widespread implementation.

The patent leverages the universal PCIe interface standard that serves multiple functions: it provides high-speed communication between CPUs, enables memory access across different processors, and supports various device types. This multi-functional approach eliminates the need for separate specialized high-speed network hardware, reducing overall system cost while maintaining high performance through a single standardized interface.

The patent implements preliminary error checking and data validation at the source before transmission begins, using PCIe's built-in error detection capabilities. This preliminary action ensures data accuracy is verified upfront, eliminating the need for intermediate response waiting during transmission. The system performs necessary validation in advance, allowing continuous high-speed transmission without pausing for accuracy verification.

The patent enables continuous data transmission through PCIe by eliminating Ethernet's stop-and-wait protocol mechanism. Data flows continuously through the PCIe interface without interruption for response acknowledgment, maintaining uninterrupted transmission streams. The system achieves continuous useful action by using PCIe's asynchronous transfer capability that doesn't require receiver acknowledgment between data packets, thereby eliminating waiting time while maintaining transmission reliability.