PCIe CPU I/O Lane Allocation via Sideband Capability Signaling
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Solution Overview
Problem
In electronics systems, particularly PCI-E systems, there is a challenge in achieving flexible and optimal lane allocation among I/O modules with varying link-width capabilities, as existing automated features like link-width negotiation and auto-bifurcation are limited, leading to suboptimal connectivity and performance.
Innovation Solution
A method involving a sideband interface for exchanging link-width capabilities between CPU and I/O modules, allowing dynamic allocation of lanes based on coded signals, enabling optimal training and bifurcation configuration to match the capabilities of each I/O module.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If link-width negotiation and auto-bifurcation features are used, then connectivity between CPU module and I/O modules is established, but the lane allocation is suboptimal and cannot achieve fully subscribed connectivity across diverse modules
Solution Approach 1:
The patent applies preliminary action by having the I/O module communicate its link-width capability to the CPU module through coded signals on the sideband interface before the lane allocation is finalized. This allows the CPU module to know the exact capabilities of each I/O module in advance and make optimal lane allocation decisions, rather than relying on post-connection negotiation that results in suboptimal configurations.
Solution Approach 2:
The patent implements feedback by using the sideband interface to create a communication loop where the I/O module provides information about its link-width capability to the CPU module, and the CPU module uses this feedback to dynamically allocate the appropriate number of lanes to each I/O module, achieving optimal lane utilization.
2Adaptability or versatility
If PCI-E switches are used to mitigate connectivity imbalance, then connectivity flexibility is improved, but the performance of the I/O module slots is degraded
Solution Approach 1:
The patent extracts the lane allocation decision-making function from the PCI-E switch and places it in the CPU module. By having the CPU module directly control lane allocation based on I/O module capabilities communicated through the sideband interface, the system eliminates the need for PCI-E switches to perform complex routing decisions, thereby maintaining I/O module slot performance while achieving connectivity flexibility.
3Extent of automation
If root complex supports auto-bifurcation, then dynamic lane allocation is enabled, but pre-configuration is still required for some root complexes, reducing ease of operation
Solution Approach 1:
The patent applies self-service by enabling the I/O module to automatically communicate its link-width capability to the CPU module through coded signals on the sideband interface. This allows the system to automatically determine and allocate the optimal lane configuration without requiring manual pre-configuration or intervention, making the system easier to operate while maintaining full automation.
Data Source
AI summary
Described are electronics systems and methods for distributing a limited number of lanes of a PCI Express-based processor (CPU) module among a plurality of PCI Express-based I/O modules with which the CPU module is in communication. The CPU module receives a code from each I/O module over a sideband interface between that I/O module and the CPU module. The coded signal represents a link-width capability of the I/O module. The CPU module is configured to allocate a link width to each I/O module based on the fixed number of lanes and the link-width capability as represented by the coded signal received from that I/O module. The link between CPU module and each I/O module is trained in accordance with the link width allocated to that I/O module.