PCI Express Credit-Based Flow Control for Deadlock Prevention
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Solution Overview
Problem
The existing PCI Express data transmission system faces issues with transmission deadlocks and increased latency due to the need for large buffers and inefficient credit management, which affects throughput and packet handling.
Innovation Solution
The system makes clients aware of available credits for each transfer type, allowing packet transmission only when sufficient credits are available, eliminating the need for FIFO buffers in the PCI Express core and introducing separate synchronization buffers for each transfer type, with the transfer type arbiter moved from the core to the application to manage credits and prioritize low-latency packets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large buffers are used in the PCI Express core to prevent deadlocks, then transmission reliability is improved, but memory requirements and device complexity increase
Solution Approach 1:
The patent extracts the buffer function from the PCI Express core and relocates it to the application side. The core no longer maintains large buffers for different transfer types, instead relying on the application to manage credits and buffer data locally. This eliminates the need for large core buffers while maintaining transmission reliability through credit-based flow control.
Solution Approach 2:
The application is empowered to self-manage data transmission by monitoring credit availability and initiating transfers only when credits are sufficient. This self-service mechanism eliminates the need for the core to buffer data, as the application autonomously ensures proper credit management and prevents deadlock conditions.
2Reliability
If large buffers are used in the PCI Express core to prevent deadlocks, then transmission reliability is improved, but device complexity increases
Solution Approach 1:
The patent extracts the buffer management complexity from the PCI Express core and transfers it to the application layer. The core is simplified to handle only credit counting and transfer arbitration, while the application manages buffering and credit monitoring. This reduces core device complexity while maintaining reliability through the credit-based protocol.
3Reliability
If FIFO buffers are used in the PCI Express core, then deadlock prevention is improved, but latency for low-latency packets increases
Solution Approach 1:
The patent segments the data path into two categories: regular transfers that use credit-based flow control through the application, and low-latency transfers that use a dedicated bypass path. This segmentation allows low-latency packets to skip the application arbitration stage and go directly from the core to the link, eliminating the latency penalty while maintaining deadlock prevention for regular transfers.
Solution Approach 2:
The patent introduces a dedicated low-latency path that acts as an intermediary channel bypassing the application arbiter. This separate path allows time-critical packets to traverse the core directly to the link interface without waiting for credit arbitration, while the application continues to manage credits for standard transfers, thus resolving the conflict between deadlock prevention and low latency requirements.
4Productivity
If the application waits for credit availability before transmission, then throughput is improved, but loss of time increases due to waiting
Solution Approach 1:
The patent implements dynamic credit management where the application continuously monitors credit availability and adapts its transmission rate accordingly. Instead of static buffering, the system dynamically adjusts the timing and rate of data transfers based on real-time credit status, allowing the application to transmit immediately when credits are available and pause only when necessary, thus minimizing waiting time while maintaining high throughput.
Data Source
AI summary
A data flow management system and method in which an application and its clients are made aware of the available credits for each type of transfer before the transfer is attempted. This enables the clients to transmit packets only when the RX side has issued a sufficient number of credits to insure that the transmission will not be stalled. The invention eliminates the need for FIFO buffers in the PCI-Express core, since the application will not transmit packets to the core until the required number of credits for the particular transfer type is available. Therefore, packet transmissions do not require buffering in the core, as they are only sent when they can be sent all the way through the core to the link. The efficient back-to-back transfer support enabled by this protocol increases the overall throughput and efficiency of the system as transfers through the application interface have fewer gaps therebetween, because the credit management protocol with its back-to-back feature reduces the idle times between packets traversing the application interface. An enhanced Quality of Service feature is also introduced by creating an environment where the low-latency packets can receive a highest attention and the lowest transmission wait time.