PCIe Cross Clock Compensation via Backpressure Ports
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Solution Overview
Problem
The differences in clock signal frequencies between the PHY and MAC layers in PCIe buses can lead to data loss or corruption due to asynchronous clocking, which existing methods attempt to address through complex looping and balancing techniques, especially in bifurcated PCIe buses.
Innovation Solution
The implementation of backpressure ports at the MAC-PHY layer interface allows for controlled reading and writing of data, decoupling the TCLK and PCLK to eliminate the need for looping and balancing, and supports various clocking schemes, including asynchronous and spread spectrum clocking, to compensate for frequency differences without using elastic buffers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex looping and balancing techniques are used to address clock frequency differences, then data integrity is improved, but device complexity increases
Solution Approach 1:
The patent extracts the clock frequency compensation function from the complex looping and balancing techniques, implementing it through a dedicated compensation value calculation and application mechanism. This separates the frequency synchronization task from the overall data transmission control, reducing design complexity while maintaining data integrity.
Solution Approach 2:
The patent changes the approach from structural complexity (looping and balancing) to parameter-based compensation. By calculating and applying compensation values based on clock frequency differences, the system achieves frequency synchronization through parameter adjustment rather than complex control logic, thereby reducing device complexity.
2Reliability
If elastic buffers are used to compensate for frequency differences, then data loss is prevented, but device complexity and resource usage increase
Solution Approach 1:
The patent extracts the frequency compensation function from elastic buffer mechanisms, implementing it through compensation values that directly adjust timing parameters. This eliminates the need for complex buffer management while preventing data loss through synchronized clock operation.
Solution Approach 2:
Instead of using resource-intensive elastic buffers, the patent employs lightweight compensation values that require minimal computational resources. These compensation parameters are calculated and applied efficiently without the overhead of buffer allocation, management, and synchronization.
3Reliability
If clock frequencies are synchronized between PHY and MAC layers, then data corruption is prevented, but adaptability to different clocking schemes decreases
Solution Approach 1:
The patent implements a universal compensation mechanism that works across multiple clocking schemes including synchronous, asynchronous, and spread spectrum clocking. The compensation value calculation adapts to different frequency relationships, providing data corruption prevention while maintaining flexibility to support various clocking configurations.
Solution Approach 2:
The patent employs dynamic compensation values that are calculated based on actual clock frequency measurements. This allows the system to adapt to different clocking schemes in real-time, adjusting the compensation parameters to match the specific frequency relationship between PHY and MAC layers, thereby maintaining both reliability and adaptability.
Data Source
AI summary
A PCIe bus adapted for cross clock compensation of asynchronous clocks includes one or more PHY data ports provided in a PHY layer having a transmit clock (TCLK) for timing data transmitted to a peripheral device and a receive clock (RCLK) for timing data received from the peripheral device, one or more media access control (MAC) ports provided in a MAC layer having an interface clock (PCLK) for timing data transmitted to the PHY layer and data received from the PHY layer, wherein the PCLK and one or both of the TCLK and the RCLK are asynchronous, and one or more backpressure ports at an interface between the PHY layer and the MAC layer for controlling reading and writing of one of the PHY layer and the MAC layer. In some aspects, the PCLK frequency is set to be always greater than a maximum frequency of the RCLK and the TCLK.