PCIe/CXL Correctable Error Counters and Leaky Buckets Against SMI Storms

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Solution Overview

Problem

PCIe and CXL devices lack internal mechanisms to count correctable errors (CEs) and inspect error rates, leading to SMI storms that cause performance degradation and make it difficult for software to track link health, necessitating a tradeoff between performance degradation and lack of insight into link integrity.

Innovation Solution

Implement a software CE counter and leaky bucket mechanism that disables CE reporting when a threshold is exceeded, allowing the BMC to perform threshold-based error rate monitoring, distinguish between persistent and temporal errors, and enable controlled CE reporting to avoid SMI storms.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If CE reporting is enabled for PCIe/CXL devices, then link health monitoring is improved, but SMI storms occur causing performance degradation

Engineering Contradiction:

Improvelink health monitoringVSAvoidsystem performance

Core Design Contradiction:

Measurement precisionVSProductivity

Solution Approach 1:

The patent implements a software CE counter that proactively counts correctable errors before they trigger SMI storms. The leaky bucket mechanism preliminarily processes and rates-limits CE reports, allowing the system to monitor link health through controlled sampling without being overwhelmed by bursts of error reports. This preliminary action prevents the harmful effect of SMI storms while maintaining monitoring capability.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces a software-based leaky bucket mechanism as an intermediary between the hardware CE reporting and the SMI handling system. This intermediary component buffers and rates-limits the flow of CE reports, transforming the direct one-to-one mapping between CEs and SMIs into a controlled, sampled reporting mechanism that prevents system overload while maintaining monitoring functionality.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If CE reporting is disabled to avoid SMI storms, then system performance is improved, but insight into link integrity is lost

Engineering Contradiction:

Improvesystem performanceVSAvoidlink integrity insight

Core Design Contradiction:

ProductivityVSLoss of information

Solution Approach 1:

The patent implements a software-based CE counter and leaky bucket mechanism that provides self-service error monitoring without requiring hardware support. The software counter autonomously tracks CEs, applies leaky bucket rate limiting, and generates controlled reports to the operating system, enabling the system to maintain performance while independently monitoring link health without external intervention or hardware modifications.

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The patent replaces the hardware-based CE reporting mechanism with a software-based implementation. Instead of relying on hardware counters and direct SMI triggers, the system uses software to count CEs, apply leaky bucket algorithms, and generate reports. This substitution allows for more flexible, configurable error monitoring that maintains system performance while providing comprehensive link integrity information.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Measurement precision

If hardware CE counting mechanism is implemented, then error tracking precision is improved, but device complexity increases

Engineering Contradiction:

Improveerror tracking precisionVSAvoiddevice architecture

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent replaces complex hardware CE counting and leaky bucket mechanisms with software-based implementations. The software counter and leaky bucket algorithm run on the host system's processor, eliminating the need for additional hardware counters, registers, and control logic in the PCIe/CXL devices. This substitution maintains error tracking precision while significantly reducing device complexity and specification requirements.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS20250238298A1Correctable error counter and leaky bucket for peripheral component interconnect express (PCIE) and compute express link (CXL) devices

Publication Date: 2025.07.24 INTEL CORP

AI summary

Embodiments described herein are generally directed to a software CE counter and leaky bucket for PCIe and CXL devices. In an example, when a burst of CEs exceeding an error threshold is reported by a PCIe or CXL device associated with a computer system, CE reporting for the device is disabled and a notification is issued to the BMC. Responsive to receipt of the notification, the BMC performs threshold-based error rate monitoring. An error counter is decremented by the BMC in accordance with a leak rate of a leaky bucket implemented by the BMC for the device. During periodic error monitoring performed by the BMC for new CEs logged by the device, the error counter is incremented when a new correctable error has been logged by the device since a prior error monitoring interval. Based on the error counter, the BMC distinguishes between persistent and temporal errors of the device.