PCIe Daisy Chain Routing for Multi-Chip Endpoint Communication

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Solution Overview

Problem

Existing computing systems face challenges in efficiently managing communication between multiple chips using Peripheral Component Interconnect Express (PCIe) due to the need for complex software intervention and address translation for multi-function endpoints, limiting compatibility and scalability.

Innovation Solution

A system-on-chip (SoC) with a multi-function endpoint controller and a centralized transaction tunneling unit that eliminates the need for software intervention by translating PCI addresses to local addresses, ensuring secure and scalable communication paths between multiple chips using PCIe.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If complex software intervention and address translation are used for multi-function endpoints, then communication between multiple chips is enabled, but system complexity and configuration difficulty increase

Engineering Contradiction:

Improvemulti-chip communication capabilityVSAvoidsoftware intervention complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent introduces a PCIe bridge device as an intermediary component between the host and multi-function endpoints. This bridge handles address translation and transaction routing automatically, eliminating the need for complex software intervention. The bridge translates PCIe addresses to local addresses and manages communication paths between multiple chips, thereby reducing system complexity while maintaining multi-chip communication capability.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The PCIe bridge device performs self-service by automatically translating addresses and routing transactions without requiring external software control. The bridge contains built-in logic to map PCIe address spaces to local address spaces and to manage communication between multiple endpoints, enabling the system to operate with minimal software intervention.

Inventive Principle:

Principle #25Self-service

2Adaptability or versatility

If custom configuration of processing subsystems is required, then specific communication needs are met, but compatibility with generic drivers is lost

Engineering Contradiction:

Improvecommunication configuration flexibilityVSAvoiddriver compatibility

Core Design Contradiction:

Adaptability or versatilityVSEase of operation

Solution Approach 1:

The PCIe bridge device is designed with universal functionality to support multiple communication configurations and endpoint types. It can handle various transaction types and address mappings through a single standardized interface, allowing generic drivers to communicate with diverse multi-function endpoints without custom configuration. The bridge adapts to different communication needs while maintaining a consistent PCIe interface.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If address translation is performed through software, then communication paths are established, but processing time and efficiency decrease

Engineering Contradiction:

Improveaddress translation capabilityVSAvoidtransaction processing time

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent replaces the mechanical/software-based address translation process with a hardware-based solution implemented in the PCIe bridge. The bridge contains dedicated translation logic that automatically converts PCIe addresses to local addresses in hardware, eliminating the time-consuming software processing steps. This hardware acceleration significantly reduces transaction processing time while maintaining full address translation capability.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS20260037473A1Enabling a Multi-Chip Daisy Chain Topology using Peripheral Component Interconnect Express (PCIe)

Publication Date: 2026.02.05 TEXAS INSTRUMENTS INC

AI summary

A system-on-chip (SoC) may be configured to enable a Multi-Chip Daisy Chain Topology using peripheral component interface express (PCIe). The SoC may include a processor, a local memory, a root complex operably connected to the processor and the local memory, and a multi-function endpoint controller. The root complex may obtain forwarding information to configure routing of transactions to one or more PCIe endpoint functions or to the local memory. The root complex may initialize, based on the forwarding information, access between a host and the one or more PCIe endpoint functions. The multi-function endpoint controller may obtain a descriptor and endpoint information to configure outbound portals for transactions to at least one remote host. The multi-function endpoint controller may establish a communication path between the host and a function out of a plurality of functions.