PCIe Inter-Device Data Exchange via External Bus Communication Port
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional data transfer methods, such as standard hardware direct memory access (DMA) engines and direct read/write access, do not support efficient transfer of large blocks of data between different hardware modules in processing systems, like GPUs, due to limitations in base address registers (BARs) that only allow small memory portions to be accessed.
Innovation Solution
A memory transfer system that includes an encoder module to embed a first address into the payload of a data packet, wrap it with a second header specifying a communication port address, and transmit it via an interconnect, allowing access to memory not exposed via PCIe BAR registers, enabling efficient transfer of large data blocks between modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If standard hardware DMA engines or direct read/write access are used for data transfer, then data transfer functionality is provided, but efficient transfer of large blocks of data is not supported due to BAR limitations
Solution Approach 1:
The patent introduces communication ports as intermediary components between PCIe devices. These ports receive data packets with embedded source addresses, enabling indirect memory access that bypasses BAR limitations. The port acts as a mediator that translates standard PCIe transactions into targeted memory access operations, allowing efficient large block transfers without requiring the source device to directly address the destination memory through constrained BARs.
Solution Approach 2:
The patent embeds the source memory address within the payload data itself, adding a new dimension of address information to the traditional data packet structure. This allows the destination device to identify and write to the correct memory location without relying on BAR-based addressing. By incorporating address information directly in the data stream, the system transcends the limitations of conventional PCIe address registration mechanisms.
2Area of stationary object
If base address registers (BARs) are used for memory access, then device memory can be accessed, but only small memory portions are accessible due to BAR size limitations
Solution Approach 1:
The patent segments the memory access function into two independent parts: the data transmission path through PCIe and the address specification path embedded in the payload. Instead of requiring a single complex BAR mechanism to handle both addressing and data transfer, the system separates these functions. The PCIe interface handles data transmission while the embedded address in the payload handles destination identification, allowing access to memory areas beyond what traditional BARs can address.
Solution Approach 2:
The patent inverts the conventional approach by embedding the address information in the payload rather than in a separate address register or BAR. Traditionally, the address is specified before data transfer; this patent specifies the address within the data stream itself. This inversion allows the memory access mechanism to bypass BAR limitations while maintaining simplicity in the PCIe interface configuration.
3Productivity
If conventional DMA or direct access methods are used, then data transfer is possible, but large block transfer efficiency is insufficient
Solution Approach 1:
The patent performs preliminary action by embedding the source address information into the payload before transmission occurs. This pre-packaging of address data within the payload eliminates the need for separate address setup operations or multiple transaction cycles. The destination device can immediately identify the correct memory location upon receiving the packet, enabling continuous high-speed transfer of large data blocks without interruption for address configuration.
Data Source
AI summary
The present disclosure relates to techniques for facilitating communication and memory transfer between PCIe devices that permit access to an entire address space even though a limited address space is exposed and/or visible via the PCIe BAR registers. To this end, the present disclosure aims to permit memory transfer of large blocks of memory from one device to another including memory invisible to the system (i.e. not exposed via PCIe BAR registers). For example, in some embodiments, a data packet may be received at a port associated with a processor interconnect. The data packet includes a header which contains a first address associated with the port. In response to identifying the first address from the first data packet at the port, the data packet is decoded. During the decoding process, a second address is identified in a payload of the data packet. The second address corresponds to a first memory location, and data associated with the payload of the data packet is then stored to the first memory location.