PCIe Data Transmission Controller Segmentation for Bus Efficiency
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Solution Overview
Problem
In storage apparatuses with multi-core processors, data transmission using direct memory access (DMA) is inefficient due to mismatched data block sizes and PCIe standards, leading to suboptimal bus performance, especially when transmitting data blocks with check codes.
Innovation Solution
A data transmission apparatus that transmits data in units of an integral multiple of the PCIe maximum payload size (256 B), using a storage system and transmission controller to handle data blocks of 520 B by dividing them into 256 B units, ensuring efficient data transfer and consistency checks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data blocks of 520 B (including check code) are transmitted directly, then data integrity is maintained through consistency checks, but PCIe bus utilization efficiency deteriorates due to size mismatch with 256 B maximum payload size
Solution Approach 1:
The patent segments the 520 B data block into multiple transmission units of 256 B each (specifically two packets: 256 B and 264 B). This segmentation allows the data to be transmitted in sizes that match the PCIe maximum payload size, thereby improving bus utilization efficiency while maintaining the ability to perform consistency checks on the original 520 B block boundary
Solution Approach 2:
The patent introduces an intermediary data structure (the 264 B packet containing remaining data and check code) that bridges the gap between the 520 B data block and the 256 B PCIe payload size. This intermediary structure enables efficient PCIe transmission while preserving data integrity verification capabilities
2Productivity
If data is transmitted in units of 256 B to match PCIe standards, then bus performance is improved, but data block structure consistency becomes complex due to division of 520 B blocks
Solution Approach 1:
The transmission process is segmented into two distinct phases: first transmitting 256 B of data, then transmitting the remaining 264 B (including check code) in a second packet. This clear segmentation simplifies the handling complexity by providing a structured approach to dividing and reassembling data blocks
Solution Approach 2:
The patent changes the transmission parameter from fixed 520 B blocks to variable-size packets (256 B and 264 B) that align with PCIe standards. This parameter change enables optimal bus performance while the receiving end uses corresponding parameter adjustments to reassemble the original data structure
3Reliability
If the last 8 B of data are transmitted separately to complete the 520 B block, then data completeness is ensured, but transmission efficiency deteriorates due to additional bus occupation
Solution Approach 1:
The patent merges the remaining data (including the critical last 8 B) with the check code into a single 264 B transmission packet. This merging ensures that all remaining data is transmitted together in one bus occupation event rather than requiring separate transmissions, thereby ensuring data completeness while minimizing bus occupation time
Data Source
AI summary
A data transmission apparatus that transmits transmission data from a first memory to a second memory through a communication channel, the first memory storing data in units of a first data block of a first data size, and the communication channel having a width of a second data size, includes: a storage that stores the transmission data read from the first memory; and a transmission controller that transmits the transmission data stored in the storage from the first memory to the second memory in units of an integral multiple of the second data size, such that data transmission from the first memory to the second memory is efficiently performed.