PCIe Device Power Management via Host-Controlled Hints
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Solution Overview
Problem
The limited low-power architecture options defined in PCIe Specifications hinder the ability to enable sophisticated system policies for power and performance optimization, as devices can only leverage a few coarse low-power states, leading to inefficient power management and performance trade-offs.
Innovation Solution
Implementing host-controlled hints for PCIe devices to enter fine-grained low-power states beyond the standard PCIe-defined states, using mechanisms like Vendor Defined Messages and Vendor-Specific Extended Capabilities to facilitate communication between the host and device for advanced power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If devices use only standard PCIe-defined low-power states (L0s, L1, L2, L3), then compliance with PCIe Specification is maintained, but power management efficiency and performance optimization are limited
Solution Approach 1:
The patent segments the coarse PCIe-defined low-power states into multiple fine-grained sub-states. For example, L1 state is divided into L1.0, L1.1, L1.2 sub-states with different power consumption and exit latency characteristics. This segmentation allows the device to select appropriate sub-states based on system policies, achieving better power management efficiency while maintaining PCIe specification compliance through the use of Vendor-Specific Extended Capabilities.
Solution Approach 2:
The patent adds a new dimension of control by introducing host-controlled hints that operate alongside the standard PCIe power state transitions. The host can provide hints about upcoming activities, enabling the device to pre-wake from lower-power sub-states when needed, thus optimizing the power-performance tradeoff without violating the standard PCIe state machine structure.
2Loss of energy
If devices enter deeper low-power states for better power savings, then power consumption is reduced, but exit latency increases
Solution Approach 1:
The patent implements preliminary action by having the host provide hints about upcoming activities before the device needs to wake up. The device can use these hints to determine whether to remain in a lighter power sub-state or enter a deeper one, pre-adjusting its power state based on predicted workload. This reduces unnecessary exit latencies while maintaining power savings when appropriate.
Solution Approach 2:
The patent makes the power state selection dynamic by allowing the device to transition between different fine-grained sub-states based on real-time conditions and host hints. Rather than statically choosing between fixed PCIe states, the device dynamically adjusts its power level within each PCIe state, optimizing the balance between power consumption and exit latency for each specific scenario.
3Productivity
If devices implement fine-grained low-power states beyond PCIe specification, then power and performance optimization is improved, but system compatibility and interoperability may be affected
Solution Approach 1:
The patent uses Vendor-Specific Extended Capabilities (VSEC) as an intermediary mechanism to expose fine-grained power state information to the host. The VSEC structure acts as a standardized interface that allows devices to communicate their advanced power management capabilities without breaking PCIe specification compliance. The host can then leverage these capabilities when supported, while maintaining compatibility with standard PCIe devices that lack such extensions.
Data Source
AI summary
Methods and apparatus for optimizing device power and efficiency based on host-controlled hints prior to low-power entry for PCI Express blocks and components. Data structures containing low-power state capability information mapping one or more fine-grained low-power states for each of at least one of an L0s, L1, L1.1, and L1.2 PCIe-defined low-power state are stored on a PCIe device coupled to a Host via a PCIe link. Messages are exchanged over the PCIe link between the Host and PCIe device to configure, using the low-power state capability information, blocks and/or components on the PCIe device to enter a fine-grained low-power state instead of an associated PCIe-defined low-power state mapped to the fine-grained low-power state when the PCIe device detects a power-change event or receives a command to enter the associated PCIe-defined low-power state. Sequences of power-level changes between multiple fine-grained low-power states may also be implemented.