PCIe Controller Direct Routing Between Address Spaces

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Solution Overview

Problem

In PCIe architectures, non-transparent bridges hinder direct data transfer between host system and device memory spaces, and lack of virtual function identification in I/O operations limits virtualization support, especially in Single Root Input/Output Virtualization (SR-I/OV) controllers.

Innovation Solution

Implementing a PCIe controller with I/O request descriptors and TLP processing hints to route data directly between host and device memory addresses, bypassing the PCIe controller's memory, and using steering tags to manage virtual functions, enabling direct data transfer and virtualization support even without device-specific virtualization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a non-transparent PCIe bridge is used to connect device to host system, then the bridge can provide internal address space and isolation, but direct data transfer between host system memory space and device memory space becomes impossible

Engineering Contradiction:
Improveaddress space isolationVSAvoiddata transfer efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the address space management by introducing separate identifier fields: one for host virtual functions and another for device virtual functions. This segmentation allows the system to maintain isolation through the non-transparent bridge while enabling direct data transfer by matching corresponding virtual function identifiers across the bridge, thus resolving the contradiction between isolation and transfer efficiency.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary mechanism in the form of paired virtual function identifier fields within I/O commands. These identifiers act as mediators that enable the non-transparent bridge to route data directly between host and device memory spaces without requiring transparency, thus maintaining isolation while enabling efficient direct transfer.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If PCIe protocol is used without virtual function identification in I/O operations, then the protocol remains simple, but I/O virtualization support is limited

Engineering Contradiction:
Improveprotocol simplicityVSAvoidvirtualization support
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent embeds virtual function identifier fields within the existing I/O command structure, nesting additional functionality inside the protocol framework. This nested approach allows virtualization support to be added without fundamentally redesigning the PCIe protocol, maintaining relative simplicity while significantly enhancing adaptability for virtualized environments.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The patent performs preliminary action by pre-establishing virtual function identifier mappings between host and device before I/O operations commence. This preliminary configuration enables the protocol to handle virtualized I/O operations efficiently without requiring complex runtime decisions, thus maintaining protocol simplicity while enabling virtualization support.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9424219B2Direct routing between address spaces through a nontransparent peripheral component interconnect express bridge
Publication Date: 2016.08.23 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US9424219B2 patent drawing
  • US9424219B2 patent drawing
  • US9424219B2 patent drawing

AI summary

A system includes a PCIe controller coupled to a device through a nontransparent PCIe bridge. The controller is operable to direct I/O operations to the device on behalf of a host system. The system also includes a PCIe driver operable within the host system to generate I/O request descriptors that specify movement of data from the PCIe controller to the host system as well as from the host system to the PCIe controller. The PCIe controller processes the I/O request descriptors and determines which device is involved in the specified movement of data. The PCIe controller generates I/O commands that contain routing information for the device (e.g., memory addresses and steering information) to route the data between the memory address of the host system and the memory address of the device, bypassing a memory of the PCIe controller.