PCI Express Data Receiver Disparity Error Removal

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The high bit error rate (BER) in PCI Express lanes leads to symbol disorder and disconnection, reducing system efficiency, as the existing technologies fail to accurately decode logic idle symbols and manage differing operating clocks between transmission and receiving ends.

Innovation Solution

A data descrambling device comprising an 8B10B decoder, a forged packet removing device, and a descrambling circuit with a linear feedback shift register (LFSR) and MUX D-type flip-flop, which determines disparity errors and corrects data signals to prevent misinterpretation of logic idle symbols and maintain data integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data is transmitted through PCI Express lanes at high speed, then bandwidth and transmission efficiency are improved, but bit error rate increases causing symbol disorder and disconnection

Engineering Contradiction:
Improvetransmission efficiencyVSAvoidbit error rate
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by detecting disparity errors in decoded data before descrambling occurs. The forged packet removing device checks for disparity errors in the decoded data stream and removes erroneous packets before they can cause symbol disorder downstream. This preventive approach maintains high transmission efficiency while eliminating reliability issues caused by high BER.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary component - the forged packet removing device - positioned between the 8B10B decoder and the descrambling circuit. This intermediary detects and removes packets with disparity errors before they propagate through the system, preventing symbol disorder while maintaining the high-speed transmission capability of PCI Express lanes.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If 8B10B decoding is performed to ensure correct symbol reception, then data integrity is improved, but disparity errors from high BER cause logic idle symbols to be misinterpreted as packet framing symbols, reducing system efficiency

Engineering Contradiction:
Improvedata integrityVSAvoidsystem efficiency
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent implements feedback by using the disparity information from 8B10B decoding to control packet removal. The forged packet removing device continuously monitors decoded data for disparity errors and uses this feedback to selectively remove erroneous packets. This ensures data integrity is maintained while preventing misinterpretation of logic idle symbols, thus preserving system efficiency.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent extracts and removes only the erroneous packets from the data stream while preserving valid data. The forged packet removing device identifies packets with disparity errors and extracts them for removal, allowing the rest of the data stream to continue processing normally. This selective extraction maintains data integrity without unnecessarily reducing system efficiency.

Inventive Principle:
Principle #2Taking out (Extraction)

3Stability of the object's composition

If elastic buffer is used to regulate data flow between transmission and receiving ends with different operating clocks, then clock synchronization is improved, but data overflow or underflow may still occur reducing transmission reliability

Engineering Contradiction:
Improveclock synchronizationVSAvoidtransmission reliability
Core Design Contradiction:
Stability of the object's compositionVSReliability

Solution Approach 1:

The patent applies preliminary action by removing packets with disparity errors before they can cause overflow or underflow conditions in the elastic buffer. By eliminating erroneous data early in the processing chain, the system maintains better clock synchronization reliability and prevents buffer overflow/underflow issues that would otherwise reduce transmission reliability.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7613959B2Data receiving apparatus of a PCI express device
Publication Date: 2009.11.03 VIA TECH INC
  • US7613959B2 patent drawing
  • US7613959B2 patent drawing
  • US7613959B2 patent drawing

AI summary

A data receiving apparatus of a PCI Express system includes a receiving device, an 8B10B decoder, a forged packet removing device, and a descrambling circuit. The forged packet removing device determines whether a disparity error occurs; and an offset removing circuit compensates a number of cycles of the lane offset. The data receiving apparatus is capable of eliminating error packet caused by framing error and preventing the problem of symbol disorder and disconnection caused by set ordered noise. Furthermore, the data receiving apparatus is also capable of removing offset.