PCI-E Peripheral DL_DOWN Reset Management for MegaRAID Controller
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Solution Overview
Problem
In PCI-E protocol-based data storage systems, warm reboots can cause cache data loss due to the DL_DOWN condition, and subsequent system resets may render MegaRAID I/O controllers inaccessible by not passing configuration information to the PCI-E core if the SERDES module's reset routine is not completed.
Innovation Solution
A PCI-E compatible device with a non-volatile memory element storing executable instructions that manage the DL_DOWN condition by selectively resetting resources, excluding cache memory and SERDES module, and ensuring the GPIO module is in a known state to prevent data loss and maintain controller recognition during reboots.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a system reset is invoked during a DL_DOWN condition, then the PCI-E SERDES module is reset, but configuration information is not passed to the PCI-E core if the reset routine is not completed, rendering the MegaRAID I/O controller inaccessible
Solution Approach 1:
The patent applies preliminary action by checking whether the SERDES module has completed its reset routine before proceeding to pass configuration information to the PCI-E core. This ensures that the controller is fully ready to receive configuration data, preventing the loss of accessibility that occurs when configuration is passed too early during the reset process.
2Reliability
If a DL_DOWN interrupt is generated during a warm reboot, then the reset mechanism is triggered, but cache data is lost due to the battery backup enable signal not being masked
Solution Approach 1:
The patent applies preliminary anti-action by masking the battery backup enable signal transition in advance before the reset sequence occurs. This counteracts the harmful effect of the enable signal transition that would otherwise cause cache data loss, preventing the problem before it can manifest during the warm reboot process.
3Adaptability or versatility
If a traditional reset mechanism with dedicated signal line is used, then reset control is precise, but the PCI-E protocol requires an in-band reset mechanism using DL_DOWN command primitive
Solution Approach 1:
The patent uses the DL_DOWN command primitive as an intermediary to trigger the reset sequence in the PCI-E protocol context. Rather than using a dedicated hardware reset signal line, the DL_DOWN command serves as a mediator that initiates the reset process through the PCI-E protocol's in-band mechanism, maintaining protocol compatibility while enabling controlled reset behavior.
Data Source
AI summary
A computing system peripheral device compatible with the peripheral component interconnect express (PCI-E) protocol responds to a DL_DOWN command primitive by configuring a general-purpose input/output (GPIO) port into a known state without invoking a GPIO module reset. In addition, select resources are excluded from resources on the peripheral device that are issued a reset command. The select resources can include a GPIO module, a memory element and a PCI-E SERDES module. After the remaining reset resources have completed their individual initialization processes, the central processor core on the peripheral device is reset. The described response to the DL_DOWN command primitive avoids cache data loss, masks signal transitions on I/O ports and timing problems that prevent some peripheral devices from being recognized in a computer's basic input/output system (BIOS).